{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

L6_ILP 2 - EE504 Lecture 6 Instruction Level Parallelism...

Info iconThis preview shows pages 1–9. Sign up to view the full content.

View Full Document Right Arrow Icon
Y. Shih “Adv Comp Org & Structures” 1 EE504 Lecture 6 Instruction Level Parallelism Part 2 Modern Superscalar Architectures and Speculative Execution Dr. Yifong Shih Northwestern Polytechnic University Spring 2008
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Y. Shih “Adv Comp Org & Structures” 2 Homework Set 4 Problem 2.5, 2.8, 2.12 due next week
Background image of page 2
Y. Shih “Adv Comp Org & Structures” 3 Outline Superscalar architectures & speculation 1. Tomasulo algorithm details 2. A Tomasulo algorithm example 3. Reorder buffers 4. Speculation in superscalars 5. Branch prediction techniques in modern superscalars 6. Some thoughts on multiple instruction issue
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Y. Shih “Adv Comp Org & Structures” 4 Basic Tomasulo Organization FP adders Add1 Add2 Add3 FP multipliers Mult1 Mult2 From Mem FP Registers Reservation Stations Common Data Bus (CDB) FP Op Queue Load Buffers Store Buffers Load1 Load2 Load3 Load4 Load5 Load6 mem
Background image of page 4
Y. Shih “Adv Comp Org & Structures” 5 Tomasulo Overview Is in-order instruction issue and out-of-order instruction completion machine using dynamic hardware scheduling Accomplishes register renaming with temporary register locations in reservation stations
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Y. Shih “Adv Comp Org & Structures” 6 Three Stages of Tomasulo Algorithm 1. ISSUE – get instruction from FP Op queue: If reservation station free (no structural hazard), the scoreboard issues instr. & send operands (with register rename ). If no active instructions intend to write this instruction’s operands, then read the registers before this instruction is issued to RS/store buffer/load buffer 2. EXECUTION – operate on operands (EX): When both operands ready then execute, if not ready, watch Common Data Bus for the result. 3. WRITE RESULT – finish execution (WB): Write on Common Data Bus to all awaiting units; Mark reservation station available. Common Data Bus Features: Regular Bus: data + destination Common Data Bus: data + source Regular = “Go To” bus; CDB = “Come From” bus
Background image of page 6
Y. Shih “Adv Comp Org & Structures” 7 Hazard Handling in Tomasulo Structural hazards occur when a functional unit (i.e. its reservation station) is busy or no load/store buffer entry is available. The issue unit stalls when a structural hazard occurs Data hazards: RAW is resolved via tags Qi, Qj & Qk. The read data will come from the RS that is going to write into the register (Qi) WAR is resolved via Qi, Qj and Qk. The read data will come either from the register or RS that is going to generate the result. The write will not affect the read. (register renaming) WAW is resolved by assigning Qi to the reservation station of the last active instruction that writes into this register. Any instructions that need the earlier write results will use Qj and Qk (register renaming) To handle control hazards, the easiest way is to stall further instruction issue until the branch decision and target address have been computed. For a better method, we can apply speculation to the basic Tomasulo algorithm (see later slides in this lecture)
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Y. Shih “Adv Comp Org & Structures” 8
Background image of page 8
Image of page 9
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}