L10_Cache - EE504 Lecture 10 Memory Hierarchy I Dr. Yifong...

Info iconThis preview shows pages 1–10. Sign up to view the full content.

View Full Document Right Arrow Icon
EE504 Lecture 10 Memory Hierarchy I Dr. Yifong Shih Northwestern Polytechnic University Spring 2008
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
New NPU School Policy Pay Attention! Effective since midterm, any student caught cheating the first time will received an ‘F’ in the course When caught cheating for the second time, the student will be expelled from NPU.
Background image of page 2
My Definition of Cheating Copying other student’s tests, homework, projects and cheat- sheets. Discussing with other students during a test. Plagiarizing publications & research papers. Project report must be in your own words. Plagiarizing information googled on the Internet. Using or helping other students with computers, cell phones, notes, textbooks and other information on a closed book test. Illegally acquiring information on test problems from other sections. I do not distinguish cheat helpers from cheaters The above rules by no means constitute a complete list; do not do things that are doubtful on your mind.
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
What I Consider OK… Discussion on homework prior to writing it down yourself Discussion on tests and solutions from a previous semester Discussion among your project partners or with other groups Any information you put on your own cheat-sheet; the information may come from any source prior to the test
Background image of page 4
Severe Deductions for… Copying solutions from an old test onto a current one.
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Outline 1. Cache introduction 2. Cache performance equations 3. 3 ways to improve cache performance 4. Improve hit rate 5. Reduce miss penalty 6. Reduce time to hit in cache
Background image of page 6
Since 1980, CPU has outpaced DRAM CPU 60% per yr 2X in 1.5 yrs DRAM 9% per yr 2X in 10 yrs •10 •DRAM •CPU Performance (1/latency) •100 •1000 19 80 20 00 90 Year Gap grew 50% per year Q. How do architects address this gap? A. Put smaller, faster “cache” memories between CPU and DRAM. Create a “memory hierarchy”.
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Generations of Microprocessors Time of a full cache miss in instructions executed: 1st Alpha: 340 ns/5.0 ns = 68 clks x 2 or 136 2nd Alpha: 266 ns/3.3 ns = 80 clks x 4 or 320 3rd Alpha: 180 ns/1.7 ns =108 clks x 6 or 648 1/2X latency x 3X clock rate x 3X Instr/clock -5X
Background image of page 8
Small, fast storage used to improve average access time to slow memory. Exploits spacial and temporal locality In computer architecture, almost everything is a cache! Registers a cache on variables First-level cache a cache on second-level cache Second-level cache a cache on memory Memory a cache on disk (virtual memory) TLB a cache on page table Branch-prediction a cache on prediction information? Proc/Regs L1-Cache L2-Cache Memory Disk, Tape, etc. Bigger
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 10
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 55

L10_Cache - EE504 Lecture 10 Memory Hierarchy I Dr. Yifong...

This preview shows document pages 1 - 10. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online