L11_Memory - Memory Hierarchy II & Virtual Memory EE504...

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EE504 Lecture 11 Memory Hierarchy II & Virtual Memory Dr. Yifong Shih Northwestern Polytechnic University Spring 2008
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Outline 1. Improving cache performance (continued) 2. Examples of caching performance 3. Main memory 4. Virtual memory concepts 5. Translation look-aside buffer
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Projects Some of you still have not decided on topics. You need to come for consultation NOW. If you cannot decide on a subject, I will give you one that you can’t refuse. Due to the size of classes, project presentations have been cancelled. Project reports are still due on the day of the final exam.
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Review: Improving Cache Performance 1. Reduce the miss rate, 2. Reduce the miss penalty, or 3. Reduce the time to hit in the cache . y MissPenalt MissRate HitTime AMAT × + =
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1. Fast Hit times via Small and Simple Caches Why Alpha 21164 has 8KB Instruction and 8KB data cache + 96KB second level cache? Small data cache and clock rate Direct Mapped, on chip
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2. Fast hits by Avoiding Address Translation CPU TLB $ MEM VA PA PA Conventional Organization CPU $ TB MEM VA VA PA Virtually Addressed Cache Translate only on miss Synonym Problem CPU $ TLB MEM VA PA Tags PA Overlap $ access with VA translation: requires $ index to remain invariant across translation VA Tags L2 $
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2. Fast hits by Avoiding Address Translation Send virtual address to cache? Called Virtually Addressed Cache or just Virtual Cache vs. Physical Cache Every time process is switched logically must flush the cache; otherwise get false hits » Cost is time to flush + “compulsory” misses from empty cache Dealing with aliases (sometimes called synonyms ); Two different virtual addresses map to same physical address I/O must interact with cache, so need virtual address Solution to aliases Use of L2, direct mapped cache Solution to cache flush Add process identifier tag that identifies process as well as address within process: can’t get a hit if wrong process
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2. Fast Cache Hits by Avoiding Translation: Index with Physical Portion of Address If index is physical part of address, can start tag access in parallel with translation so that can compare to physical tag Limits cache to page size: what if want bigger caches and uses same trick? Higher associativity moves barrier to right Page coloring Page Address Page Offset Address Tag Index Block Offset
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3: Fast Hits by pipelining Cache Case Study: MIPS R4000 8 Stage Pipeline: IF–first half of fetching of instruction; PC selection happens here as well as initiation of instruction cache access. IS–second half of access to instruction cache. RF–instruction decode and register fetch, hazard checking and also instruction cache hit detection. EX–execution, which includes effective address calculation, ALU operation, and branch target computation and condition evaluation.
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L11_Memory - Memory Hierarchy II & Virtual Memory EE504...

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