Midterm answer - EE504C Midterm Exam Spring 2008 Problem 1...

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EE504C Midterm Exam Spring 2008 Problem 1 (25 points) A basic Tomasulo machine has fetched eight instructions into its instruction window/operation  queue (see table below.) Inst window Instruction  0 (head of  queue) ADD R1, R2, R3  1 SUB  R4, R1, R3 2 MUL R4, R2, R3 3 LW R2, 8(R1) 4 BEQ R7, R8, NEXT 5 ADD R1, R1, R2 6 SW R2, 12(R1) 7 DIV R2, R2, R3 This machine has 5 functional units: adder1, adder2, mult1, div1 and branch unit.  There is also  a load/store buffer that has six entries. (a) Assume that each functional unit or load/store unit takes more than ten cycles to  complete execution.  Further assume the issue unit is able to issue as many instructions  to functional units and load/store buffer as it pleases in one cycle, subject to the normal  Tomasulo constraints.  Moreover, the values of R1 and R2 are in the registers initially  before any instructions are issued.  Fill in the fields of reservation stations in the  following table after 1 cycle. (10 points) Adder1 Adder2 Mult1 Div1 branch Qj 0 Adder1 0 0 Qk 0 0 0 0 Vj (R2) (R2) (R7) 1
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Vk (R3) (R3) (R3) (R8) A NEXT ANS: the second ADD cannot issue because we’ve run out of adders.  Because of in-order  issue, neither SW nor DIV can issue in the first cycle. (b) Fill the RegisterStat table after 1 cycle. (5 points) R1 R2 R3 R4 R5 R6 R7 R8 Qi Adder1 L/S 0 MULT1 (c) Fill in the load/store buffer after 1 cycle. (5 points) Buffer number Load/store instruction
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This note was uploaded on 01/19/2011 for the course EE EE504 taught by Professor Drlao during the Fall '10 term at College of the North Atlantic.

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Midterm answer - EE504C Midterm Exam Spring 2008 Problem 1...

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