Unformatted text preview: Problem 2: A program containing the following two instructions are run through the MIPS 5-stage pipeline. … Lw r4, 0(r1) Sw r2, 0(r4) … Draw a pipeline timing diagram to explain how to forward data from lw to sw. ANS: A mandatory stall cycle must be inserted between load and store before r4 data from load can be forwarded from MEM/WB pipeline register to the input of ALU of the store instruction....
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This note was uploaded on 01/19/2011 for the course EE EE504 taught by Professor Drlao during the Fall '10 term at College of the North Atlantic.
- Fall '10