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Quiz 7 answer - Memory reference Hit or miss Set/slot...

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EE504C Quiz 7 Spring, 2008 A CPU uses 32 bits for addressing. The processor generates a memory reference sequence shown in order in the table below. The references go to a 16-entry two-way set associative cache containing lines each of 16 bytes in length. Use your knowledge of the set associative cache, fill in the remaining columns in the table.
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Unformatted text preview: Memory reference Hit or miss? Set/slot number Way 0 or way 1? New tag Addr of evicted line 3DE0,781C miss 1 3DE0,78 none 4FFF,FEF0 miss 15 4FFF,FE none 0000,0000 miss 0000,00 none 0000,6668 miss 6 0000,66 none ABCD,ABC4 miss 13 ABCD,AB none ABCD,AF04 miss 1 ABCD,AF none 4FFF,FEF0 hit 15 same none 0000,0000 hit same none...
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