Quiz 8 answer - (b What is the page offset for all four...

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EE504C Quiz 8 Spring 2008 A demand-paging CPU supports 32-bit virtual addressing and 32-bit physical addressing.  The  page size is 4 KB.  The virtually indexed, physically tagged L1 cache has 1,024 entries of 16- byte data lines.  The CPU has generated the following four virtual addresses: FEDC,BA24;  0000,5A24; AAAA,0A24 and D0D0,3A24.  Answer the following questions.  To get any credit,  you must explain all your work. (a) What is the byte offset for all four addresses? ANS: 4
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Unformatted text preview: (b) What is the page offset for all four addresses? ANS: A24 (c) What are the cache indices? Virtual address Cache index (hex) FEDCBA24 BA2 00005A24 5A2 AAAA0A24 0A2 D0D03A24 3A2 (d) What virtual addresses are synonyms? ANS: FEDC,BA24 and D0D0,3A24 (e) If all four virtual pages map into the same physical page number of 12345 (hex), what is the physical address? ANS: 1234,5A24...
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This note was uploaded on 01/19/2011 for the course EE EE504 taught by Professor Drlao during the Fall '10 term at College of the North Atlantic.

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