ee488_cpu_intro_r3 - Northwestern Polytechnic University...

Info iconThis preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon
N orthwestern P olytechnic U niversity EE488 Lecture Notes CPU Basics Introduction to the NPU CPU
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EE488 - NPU Lecture Goals 9 Understand the microarchitecutre 9 Understand the basic CPU components 9 Understand the 5 basic steps to execute an instruction 9 Understand multi-cycle clocking 9 Understand the term “optimal performance”
Background image of page 2
What is a CPU? EE488 - NPU CPU’s, in their simplest form, execute instructions sequentially. Sequential execution can be altered by interrupts (traps) or program branching. This course will focus on a simplified RISC architecture based on the DLX design which is based on the popular MIPS processor. This DLX is CPU studied in the reference text book. The DLX is the most studied CPU in the world! Our CPU will be referred to as the “NPU” CPU and will undergo 3 iterations during the course. Revisions 1 through 3 Our goal is to study the inner workings (this is what counts).
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
The Micro-architecture Level EE488 - NPU Micro-architecture defines the internal layout of the CPU. This level is always unique. CPU’s can change this dramtically from one revision to the next without altering the effect on software. Studying the internals of a complex chip is very similar to studying the external components in a computer. Internal bus External bus
Background image of page 4
CPU Basic Components EE488 - NPU All CPU’s contain these mimimum components . PC (Program Counter) Address pointer of next instruction to be executed IR (Instruction Register) Holds current instruction to be executed Decode and Control Logic Logic that determines the instruction type and controls all logic needed to complete the instruction. ALU (Arithmetic Logic Unit) Logic that performs the actual execution of the instruction. BIU (Bus Interface Unit) This logic handles all interfacing between the CPU and external components such as reading and writing memory. Temporary Storage Registers Holds temporay data for instruction exection or used as a pointer for where data is or used for any other temporary purpose.
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CPU Basic Components EE488 - NPU A 32-bit CPU means this is the main data bus size of the internal data path. The O/S is designed around this fact. Note: IA-32 and new EM64T Architecture Designs… Decode and Control PC IR ALU 0 31 R0 R1 R2 R3 R4 BIU temporay storage registers 32 32 32 Address Function 0 31 Data MEMRD# MEMWR# ADS#
Background image of page 6
Executing an Instruction EE488 - NPU ¾ Instruction execution can be divided into several steps.
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 8
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 01/19/2011 for the course EE EE448 taught by Professor Drlaw during the Summer '10 term at College of the North Atlantic.

Page1 / 27

ee488_cpu_intro_r3 - Northwestern Polytechnic University...

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online