ee488_datapath_r2 - Northwestern Polytechnic University...

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N orthwestern P olytechnic U niversity EE488 Lecture Notes Data Path Development (NPU CPU rev.1)
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EE488 - NPU Lecture Goals 9 Understand the data path of a CPU. 9 Understand how each instruction format flows in the data path. 9 Understand that the instruction set (formats) dictates the data path design. 9 How to view a data path and determine how you can enhance it. 9 What is the cost of enhancing the data path.
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The Data Path EE488 - NPU The data path is the part of the CPU that contains the ALU and all the inputs and outputs that connect to it. Analogy is like driving your car on the road. You can drive on residential streets slowly or hop on the highway and drive fast. No matter where you drive there are rules and speed limits. The data path determines how an instruction is executed (from start-to-finish). The design of the CPU’s data path has a direct effect on the CPU’s performance. The data path typically undergoes many enhancements in the life of the CPU. The only restriction is that changes made does not effect the existing instruction set. This allows previous compiled programs to still be executed.
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EE488 - NPU The Data Path Once the decode logic understands the current instruction, it starts the process of executing it. The execution of instructions take part in the data path . SE Rs1 Opc Rd imm IR 16 32 ALU
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The NPU CPU Data Path
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The Data Path EE488 - NPU To best understand the data path we can observe how each instruction type is executed. Group all of the instructions into common categories (which should fit the instruction formats). Careful review of the NPU CPU instruction set reveals the following instructions are unique.
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Building the Data Path In the following slides we will see the logic needed to execute each particular instruction format. Each of the unique instruction types will be reviewed until we have a complete data path to execute all of our instructions. By observing how each unique instruction is executed and what logic and paths are required will give us a good understanding of how a CPU executes instructions. More importantly it will allow us to understand strengths and weaknesses and make modifications in future generations of our CPU.
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The IF Process EE488 - NPU PC register holds address that points to next instruction NPC is the Next address that will be loaded into The PC register PC refers to the current address that is held in the PC register. One input is fixed At 4 to create the PC = PC + 4 (NPC) The fetched instruction is loaded into a register called the instruction register (IR). MEMRD The current PC value is fed back to the adder to automatically increment and point to the next instruction This block represent memory where the instructions are located. The instruction memory is commonly used to distinguish the fact that this specific area of memory has program instructions.
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All instructions must be fetched (IF) and decoded (ID) PC INSTR. MEM
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ee488_datapath_r2 - Northwestern Polytechnic University...

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