ee488_logic_supp1 - NPU EE488 Computer Architecture and...

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EE488.delay.1 @NPU 2005 NPU EE488 Computer Architecture and Engineering Review Technology & Delay Modeling Lecture slides adapted from Dave Patterson (http.cs.berkeley.edu/~patterson)
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EE488.delay.2 @NPU 2005 Outline of Supplemental Lecture ° Review ° ISA, Performance Wrap-up ° Performance and Technology ° Delay Modeling and Gate Characterization ° Clocking Methodologies and Timing Considerations
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EE488.delay.3 @NPU 2005 Review: Aspects of CPU Performance CPU time = Seconds = Instructions x Cycles x Seconds Program Program Instruction Cycle CPU time = Seconds = Instructions x Cycles x Seconds Program Program Instruction Cycle instr count CPI clock rate Program X Compiler X X Instr. Set X X Organization X X Technology X
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EE488.delay.4 @NPU 2005 Amdahl's Law Speedup due to enhancement E: ExTime w/o E Performance w/ E Speedup(E) = -------------------- = --------------------- ExTime w/ E Performance w/o E Suppose that enhancement E accelerates a fraction F of the task by a factor S and the remainder of the task is unaffected then, ExTime(with E) Š ((1-F) + F/S) X ExTime(without E) Speedup(with E) Š 1 (1-F) + F/S
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EE488.delay.5 @NPU 2005 Range of Design Styles Cu stom C ontrol Logic Custom Register File Custom Design Standard Cell Gate Array/FPGA/CPLD Standard ALU Standard Registers Gates Gates Routing Channel Gates Routing Channel Gates Custom ALU Performance Design Complexity (Design Time) Longer wires Compact
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EE488.delay.6 @NPU 2005 Basic Technology: CMOS ° CMOS: Complementary Metal Oxide Semiconductor • NMOS (N-Type Metal Oxide Semiconductor) transistors • PMOS (P-Type Metal Oxide Semiconductor) transistors ° NMOS Transistor • Apply a HIGH (Vdd) to its gate turns the transistor into a “conductor” • Apply a LOW (GND) to its gate shuts off the conduction path ° PMOS Transistor • Apply a HIGH (Vdd) to its gate shuts off the conduction path • Apply a LOW (GND) to its gate turns the transistor into a “conductor” Vdd = 5V GND = 0v Vdd = 5V GND = 0v
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EE488.delay.7 @NPU 2005 Basic Components: CMOS Inverter Vdd Circuit ° Inverter Operation Out In Symbol Out In PMOS NMOS Vin Vout Vdd Vdd Vdd Vdd Vdd Out Open Discharge Open Charge
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EE488.delay.8 @NPU 2005 Basic Components: CMOS Logic Gates NOR Gate NAND Gate ABO u t 00 1 01 1 10 1 11 0 u t 1 0 0 0 Out A B A B Out Vdd A B Out Vdd A B Out
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EE488.delay.9 @NPU 2005 Gate Comparison Vdd A B Out Vdd A B Out NAND Gate NOR Gate ° If PMOS transistors is faster: • It is OK to have PMOS transistors in series • NOR gate is preferred • NOR gate is preferred also if H -> L is more critical than L -> H °
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This note was uploaded on 01/19/2011 for the course EE EE448 taught by Professor Drlaw during the Summer '10 term at College of the North Atlantic.

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ee488_logic_supp1 - NPU EE488 Computer Architecture and...

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