ee488_memory_4 - Northwestern Polytechnic University EE488...

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N orthwestern P olytechnic U niversity EE488 Lecture Notes Computer Memory Technologies
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EE488 - NPU Lecture Goals 9 Understand memory heirarchy 9 Understand basic memory technology 9 Understand bit cell size 9 Understand read vs. write access times 9 Understand how DRAM maintains it’s high performance
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CPU Speed and Size EE488 - NPU Processor speeds are significantly faster than system memory.
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CPU vs. Memory Speeds EE488 - NPU
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Memory Technologies EE488 - NPU Where do these memories fit and why? Magnetic
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Memory Technologies EE488 - NPU •M a i n M e m o r y – DRAM technology (capacitor storage) Cache Memory (L1, L2. ..) – SRAM technology (transistor storage) System BIOS – Flash, EEPROM technology (floating gate storage) Disk Storage – Rotating memory (magnetic storage)
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Computer Memory Overview EE488 - NPU Registers Cache L1 CPU Cache L3 Main Memory System BIOS Disk Drive Registers Static RAM Dynamic RAM (DRAM) Cache L2 At power-on, BIOS enables the basic computer components and verifies DRAM is OK. Then it loads The OS into memory which takes over. Magnetic storage ROM (Flash or EEPROM) 1 2 Once the OS is loaded into memory it takes over full control of the computer
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Read-Only Memory “ROM”
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Read Only Memory (ROM) EE488 - NPU ROM memory is typically only read during normal operation and not written too. High read to write ratio •R O M s a r e non-volatile” meaning they retain their contents over a power cycle . •T h e r e a r e five basic ROM types: ROM : “Read Only Memory” – (Masked ROM) Programmed by manufacturer PROM : “programmable read-only memory” 1 time programmable by user EPROM : “Erasable programmable read-only memory” Re-write many times (erasable by UV light) EEPROM : “Electrically” erasable/programmable ROM Byte erasable, good read, poor write speeds FLASH : Flash memory works much faster than traditional Block erasable, usually 512 bytes in size.
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ROM Block Diagram EE488 - NPU 16x8 ROM A3 D7 D6 A2 D5 A1 D4 D3 A0 D2 D1 CS D0 OE ROMs are simple addressing devices. To read any address place the address of the location you want to read and assert the CS and OE signals. data Old Address New Address A[3:0] t ACC CS OE Data t OE
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Masked “ROM” EE488 - NPU Programmed by manufacturer (using a photo-mask) These masks are very exepensive to create Must create many masked parts to get cost benefits. Once programmed, NO going back (permanent!) If you have a bug, then you have lot’s of parts with bugs! Not good for development, only for “refined” high volume Not cost effective for low volumes KEY = Very cost effective for high volumes.
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EE488 - NPU Programmable “PROM” PROM technology was developed in 1970 (Harris Semiconductor) Uses a ”fusible-link” technology.
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ee488_memory_4 - Northwestern Polytechnic University EE488...

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