ee488_npu_instr_set_r3 - Northwestern Polytechnic...

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N orthwestern P olytechnic U niversity EE488 Lecture Notes NPU CPU Instruction Set
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EE488 - NPU Lecture Goals 9 Understand the decode process 9 Understand the NPU instruction set 9 Understand what are instruction formats 9 Understand machine code 9 Understand the term load/store
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EE488 - NPU CPU Basics Review ¾ Once we get a new instruction how do we execute it? ¾ New instructions are placed in the IR register. ¾ The decode logic must first determine the “instruction format ”. ¾ The instruction format tells the decode logic how to decipher the details of the instruction ± such as the opcode, and operands (source and destination registers, etc). ± The instruction set limits compatibility! ¾ Once the decode logic knows how to read the instruction it then provides all the neccessary controls to execute the instruction. ¾ What are these instructions that the decode logic recognizes?
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EE488 - NPU NPU CPU Overview • There are 32 32-bit GPR registers (floating-point is not incuded) • Typically some registers have hardware restrictions i.e. R0 is always 0 and R31 is used as a return address register • Generally, software is free to use the registers any way it wants The O/S is in control of these definitions.
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Accessing System Memory EE488 - NPU ¾ The instruction set only provides 2 methods to access memory . ± LW (Load Word) Read a word (32-bits) from system memory ± SW (store word) Write a word (32-bits) to system memory ¾ The LW and SW are the only methods the CPU has to read and write system memory. ± The instruction set can be expanded to include additional memory access commands such as. .. LH (load high) : read 16-bits from memory SH (store high) : write 16-bits to memory LB (load byte) : read 8-bits from memory SB (store byte) : write 8-bits from memory
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Loading Data into Registers EE488 - NPU ¾ The NPU CPU is a load/Store Architecture. ± All resources must be in the CPU before the command can be
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ee488_npu_instr_set_r3 - Northwestern Polytechnic...

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