ee488_npu_pipeline_5 - Northwestern Polytechnic University...

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N orthwestern P olytechnic U niversity EE488 Lecture Notes Pipelining (NPU CPU rev.2)
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EE488 - NPU Lecture Goals 9 Understand Pipelining 9 Understand Hazards caused by Pipeline 9 Understand Latency and Throughput 9 Understand the importance of Branch Prediction. 9 Understand Pros and Cons of extending pipeline
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Quick Review NPU CPU rev.1 EE488 - NPU NPU CPU is derived from the popular DLX RISC design. It is a single instruction issue 32-bit design 32 general purpose registers (R0-R31) R0 is always 0 All instructions are fixed 32-bit length All opcodes are 6-bits wide (fixed length) Supports 3 main instruction formats (R, I and J-type) Optimum execution is 1 instruction every 5 clock cycles.
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NPU CPU (rev.1) Architecture EE488 - NPU IR Decode CTL REGS RS1 SE 16/26 32 ALU ZERO ADD DATA MEM PC INSTR. MEM ADD +4 MEMRD PC+4 MEMWR IF ID EX WB MEM MEMRD Branch Address Branch Address Jump Address
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Timing Basics EE488 - NPU CPU is designed to use 5 step instruction execution process. Each “step” takes a specific amount of time to complete. (Assume the following timings for the NPU CPU rev.1) IF = 2ns ID = 1ns EX = 2ns MEM = 2ns WB = 1ns To ease the design, each step is made to take the same amount of time which is determined by the slowest step. This is a fixed “ multi-cycle ” execution unit with each stage taking 2ns. Note: “ single-cycle ” means everything is completed in 1clock cycle (1 very long clock!).
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Timing Analysis of an LW-type instruction
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EE488 - NPU LW R21,0x3200(R0) IR Decode CTL REGS RS1 ID EX MEM WB IF ALU ZERO DATA MEM PC INSTR. MEM ADD +4 MEMRD PC+4 Branch Address Branch Address MEMWR MEMRD 16/26 32 ADD SE 2ns Total Execution Time = 2ns
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EE488 - NPU LW R21,0x3200(R0) IR Decode CTL REGS RS1 16/26 32 ALU ZERO DATA MEM PC INSTR. MEM ADD +4 MEMRD PC+4 IF EX MEM WB ID Branch Address Branch Address MEMWR MEMRD ADD SE 2ns Total Execution Time = 4ns
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EE488 - NPU LW R21,0x3200(R0) IR Decode CTL REGS RS1 IF ID MEM WB EX ALU ZERO DATA MEM PC INSTR. MEM ADD +4 MEMRD PC+4 Branch Address Branch Address MEMWR MEMRD 16/26 32 ADD SE 2ns Total Execution Time = 6ns
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EE488 - NPU LW R21,0x3200(R0) IR Decode CTL REGS RS1 IF ID EX WB ALU ZERO DATA MEM PC INSTR. MEM ADD +4 MEMRD PC+4 MEMWR MEM MEMRD Branch Address 16/26 32 Branch Address ADD SE 2ns Total Execution Time = 8ns
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LW R21,0x3200(R0) EE488 - NPU IR Decode CTL REGS RS1 IF ID EX MEM WB ALU ZERO DATA MEM PC INSTR. MEM ADD +4 MEMRD PC+4 Branch Address Branch Address MEMWR MEMRD 16/26 32 ADD SE 2ns Total Execution Time = 10ns
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EE488 - NPU Execution time for LW instruction (timing example) The NPU CPU rev.1 can execute an instruction every 10ns . If each clock cycle is fixed at 2ns then we can “
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ee488_npu_pipeline_5 - Northwestern Polytechnic University...

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