ee488_superscalar_2 - Northwestern Polytechnic University...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
N orthwestern P olytechnic U niversity EE488 Lecture Notes SUPERSCALAR (NPU CPU rev.3) SuperScalar NPU CPU rev.3 SuperScalar NPU CPU rev.3
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
What is Superscalar? EE488 - NPU Increasing the pipeline depth eventually leads to diminishing returns. – longer pipelines take longer to re-fill – data and control hazards become more complex • (reducing the performance advantages) A solution is a Dynamic Multi-Issue processor – issue more than one instruction per clock cycle – current pipeline design can only issue 1 instr/clock Such processors are Superscalar processors – basically consists of multiple parallel pipelines
Background image of page 2
The Basic Idea? EE488 - NPU (scalar pipeline design) IF ID Issue maximum 1 instruction per clock EX MEM WB ( Superscalar pipeline design) IF ID EX MEM WB Issue maximum 2 instruction per clock IF ID EX MEM WB
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Characteristics of Superscalar EE488 - NPU Issue more than 1 instruction per clock – Typycally between 2 to 8 instructions Instructions are fetched and decoded in-order but can be executed out-of-order ( OOE ). – Decode/control logic determines best order to issue – decode and control logic complexity increases – hazards become more complex – Data hazards are no longer trivial. – branch prediction becomes more critical. Instructions are written back in-order – processor complexity significantly increases due to the need to keep track of everything. – must make sure program behavior is not altered!
Background image of page 4
EE488 - NPU Pipeline can issue 1 new instruction every clock cycle Optimum performance occurs when no hazards are encountered. Clocks per instruction (CPI)
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 6
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 22

ee488_superscalar_2 - Northwestern Polytechnic University...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online