l12_ece15a_6

l12_ece15a_6 - Steering Logic Use of...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ECE 15A Fundamentals of Logic Design Lecture 12 Malgorzata Marek-Sadowska Electrical and Computer Engineering Department UCSB 2 Steering Logic Use of Multiplexer/Demultiplexer in Digital Systems So far, we've only seen point-to-point connections among gates Mux/Demux used to implement multiple source/multiple destination interconnect A B Z Y Multiplexers Demultiplexers 3 Multiplexers ± This block performs the function of selecting one of the data inputs to appear at the output dependent on the state of some binary coded control inputs. ± Eg. A 4 way multiplexer will have 2 control bits C0 and C1 and output function ± Q=C 0’C1’D0+C0’C1D1+C0C1’D2+C0C1D3 D0 D1 D2 D3 C0 C1 Q Data Output Data Inputs Control Inputs D0 D1 D2 D3 C0 C1 Q 4 Multiplexer: Example S1 S0 Y 0 0 D0 0 1 D1 1 0 D2 1 1 D3 S0 and S1 are decoded to select a particular AND gate. S0 S1 D0 D1 D2 D3 Y 5 Use of Multiplexers/Selectors Multi-point connections MUX MUX DEMUX A B Sum A0 A1 B0 B1 Sa Sb Ss S0 S1 Multiple input sources Multiple output destinations 6 I 1 0 0 0 0 1 1 1 1 I 0 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 Z 0 0 1 0 0 1 1 1 A 0 1 Z I 0 I 1 Multiplexers/Selectors 2 data inputs, n control inputs, 1 output used to connect 2 points to a single point control signal pattern form binary index of input connected to output n n Two alternative forms for a 2:1 Mux Truth Table Z = A' I + A I 01 Functional form Logical form
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 7 Multiplexers/Selectors Z = A' I + A I 01 Z = A' B' I0 + A' B I1 + A B' I2 + A B I3 Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 + A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7 In general, Z = Σ m I 2 -1 n k=0 k k in minterm shorthand form for a 2 :1 Mux n 2:1 mux I 0 I 1 A Z I 0 A I 1 I 2 I 3 B Z 4:1 mux I 0 A I 1 I 2 I 3 B Z 8:1 mux C I 4 I 5 I 6 I 7 8 Multiplexer/Selector Large multiplexers can be implemented by cascaded smaller ones Alternative 8:1 Mux Implementation 0 1 S 0 1 S 0 1 S 0 1 S 0 1 S1 2 3 S0 C AB I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 C C C Z 4:1 mux 4:1 mux 8:1 mux 2:1 mux 0 1 2 3 0 1 2 3 S S 1 S 0 S 1 S 0 Z A C B I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 0 1 9
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 01/20/2011 for the course ECE 15A taught by Professor M during the Winter '08 term at UCSB.

Page1 / 5

l12_ece15a_6 - Steering Logic Use of...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online