Project1_HDL_examples

# Project1_HDL_examples - Copyright 1996 by Doone...

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//------------------------------------------------------------ // Copyright 1996 by Doone Publications. All rights reserved. // // Design: ALU // Name: Doug Smith // Date: 1st June 1996 // // Description: // ALU with separate Logic Unit, Arithmetic Unit // and Shifter Unit. //------------------------------------------------------------ module ALU (Sel, CarryIn, A, B, Y); input [4:0] Sel; input CarryIn; input [7:0] A, B; output [7:0] Y; reg [7:0] Y; reg [7:0] LogicUnit, ArithUnit, ALU_NoShift; always @(Sel or A or B or CarryIn) begin: ALU_PROC //------------ // Logic Unit //------------ case (Sel[1:0]) 2'b 00 : LogicUnit = A & B; 2'b 01 : LogicUnit = A | B; 2'b 10 : LogicUnit = A ^ B; 2'b 11 : LogicUnit = ! A; default : LogicUnit = 8'b X; endcase //----------------- // Arithmetic Unit //----------------- case ({Sel[1:0], CarryIn}) 3'b 000 : ArithUnit = A; 3'b 001 : ArithUnit = A + 1; 3'b 010 : ArithUnit = A + B; 3'b 011 : ArithUnit = A + B + 1; 3'b 100 : ArithUnit = A + ! B; 3'b 101 : ArithUnit = A - B; 3'b 110 : ArithUnit = A - 1;

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Project1_HDL_examples - Copyright 1996 by Doone...

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