EE118Lab - EE118 Spring 2009 SAN JOSE STATE UNIVERSITY...

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EE118 Spring 2009 SAN JOSE STATE UNIVERSITY DEPARTMENT OF ELECTRICAL ENGINEERING Course Information (Greensheet) COURSE: EE118 - Digital Logic Design (Digital Design I) Lecture - Mon, Wed, 9am 10:15pm, ENG345 Lab - Coordinated by Prof. Choo, and taught by Lab Instructors TAUGHT BY: Prof. C. Choo, ENG 253, 924-3980, [email protected] OBJECTIVES: To provide a thorough background, at the introductory level, of the logical (mathematical) and electrical basis for digital system design. Major building blocks for designing digital systems will be examined and used which include gates, MUXes, DEMUXes, decoders, encoders, comparators, various arithmetic blocks, flip-flops, counters, registers, RAMs/ROMs, PLDs and FPGAs. Students will also learn to design digital circuits using schematic and Hardware Description Language (HDL), particularly, Verilog. This course is the gateway to all other digital system courses in the curriculum. ABET-Compliant Learning Objectives: 1) The ability to understand the number system, including binary, octal and hexadecimal numbers, and 2’s complement number representation. 2) The ability to understand Boolean algebra and to apply various Boolean theorems to prove Boolean identities and to simplify Boolean functions. 3) The ability to understand the transistor-level structure of TTL and CMOS logic gates and their electrical and timing characteristics. 4) The ability to construct the K-map from a Boolean expression and to find the minimal SOP/POS forms. 5) The ability to understand Quine-McCluskey algorithm, i.e., to construct the Q-M table, to perform matching iterations to find PIs, and to find essential PIs by either detecting dominance relations or using Patrick function to corresponding Boolean expression. 6) The ability to design moderately complex arithmetic and logic circuits including carry lookahead adder, BCD adder, comparator, multiplier, and to evaluate the resulting performance in terms of gate count and propagation delay. 7) The ability to understand the working of MSI devices including decoders, encoders, and multiplexers, and to design various logic circuits using them. 8) The ability to analyze cross-coupled gates and to identify any metastability. 9) The ability to understand the behavior, timing issues, and internal
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structure of various flip-flops (RS, JK, D and T) and registers. 10) The ability to identify and prevent various hazard and timing problems. 11) The ability to analyze and design various flip-flop-based state machines (synchronous sequential circuits), including counters and one-hot controller. 12) The ability to understand how PLA, ROM, and modern FPGA work and how to use them to design complex logic circuits. 13) The ability to understand the basics of HDL language, to write a HDL program for various logic circuits and to test their functionality and timing.
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This note was uploaded on 01/22/2011 for the course EE 118 taught by Professor Staff during the Spring '08 term at San Jose State.

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EE118Lab - EE118 Spring 2009 SAN JOSE STATE UNIVERSITY...

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