ee270_syl_F10

ee270_syl_F10 - San Jose State University Department of...

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Page 1 San Jose State University Department of Electrical Engineering EE270 - Advanced Logic Design Instructor: Tri Caohuu Office Location: ENGR 375 Telephone: (408) 924-3951 Email: tri.caohuu@sjsu.edu Office Hours: Tuesday: 15:00 to 17:30,Wenesday: 14:00 to 16:30 Class Days/Time: TR 18:00-19:15 Class Room: E 303 Laboratory: Open Lab E389/E291 Course Description: This course presents principles and techniques in logic design: design and analysis of combinational logic circuit; flip-flop properties, sequential circuit analysis and synthesis, algorithmic state machines; asynchronous circuit design and analysis; and design for testability. The students are required to do exercises and a design project in the open laboratory using HDL-based methodology. The course is intended for senior students and beginning graduate student in the digital design concentration. Course Goals and Student Learning Objectives: This course aims at providing students with fundamentals concepts and design techniques in synchronous circuit design, asynchronous circuit design and design for testability. Students will firstly learn to analyze and synthesize synchronous digital circuits including techniques to reduce of state table and to make optimal state assignment. In the second part students will learn both Huffman and Muller types of asynchronous circuit and will be introduced to asynchronous design techniques. In the final part, students will be introduce to fundamentals and techniques in design for testability (DFT) Course Content Learning Outcomes : Upon successful completion of this course, students will be able to: 1. CLO1:Understand fundamental concepts of synchronous circuit design (a) 2. CLO2: Perform simplification of switching functions (c)
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ee270_syl_F10 - San Jose State University Department of...

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