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Unformatted text preview: EE 270 Project Due May 13th, 2009 Design a circuit that meets the following specifications: The circuit has two inputs: a clock input c and a control input w. The output, z, replicates the clock pulse when w=1; otherwise z=0. The pulses appears on z must be full pulses. Consequently if c=1 when w changes from 0 to 1, then the circuit will not produce a partial pulse on z, but will wait until the next clock pulse to generate z=1. If c=1 when w changes from 1 to 0 then a full pulse must be generated; that is, z=1 as long as c=1. The following waveform illustrates the desired operation: c w z 1. Design, simulate and synthesis the circuit using synchronous sequential logic. You may use either VHDL or Verilog. However, structural modeling must be used; as you will design by hand first, then enter the design for simulation and synthesis purpose. 2. Repeat Part 1, using asynchronous sequential logic. You design should focus on minimum circuit implementation 3. Compare the two approaches a. Level of difficulty in designing b. Area and time (use Toshiba Lib ‐ Synopsys) c. Power (use Toshiba Lib ‐ Synopsys) 4. You may work in team of 2. The project report should includes the following items: a. Title page: Names and distribution of work b. Paper‐and‐pencil designs c. HDL coding and test‐bench d. Simulation results e. Synthesis results f. Comparison and analysis g. Conclusion ...
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