Lecture_7 - ECE 331 Digital System Design Karnaugh Maps and...

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ECE 331 – Digital System Design Karnaugh Maps and Logic Circuit Minimization
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ECE 331 - Digital System Design 2 Karnaugh Maps Graphical representation of a truth table - Can be used to minimize logic functions Uses logic adjacency Does not produce unique results Not directly transferable to computer algorithms Why not just use Boolean Algebra? - Boolean algebra is useful for general proofs - Difficult to use for minimization
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ECE 331 - Digital System Design 3 x 2 (a) Truth table (b) Karnaugh map 0 1 0 1 m 0 m 2 m 3 m 1 x 1 x 2 0 0 0 1 1 0 1 1 m 1 m 3 m 2 x 1 Two-variable K-Map Row # 0 1 2 3 MSB LSB
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ECE 331 - Digital System Design 4 x 1 x 2 x 3 00 01 11 10 0 1 (b) Karnaugh map x 2 x 3 0 0 0 1 1 0 1 1 m 0 m 1 m 3 m 2 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 m 4 m 5 m 7 m 6 x 1 (a) Truth table m 0 m 1 m 3 m 2 m 6 m 7 m 4 m 5 Three-variable K-Map 0 1 2 3 4 5 6 7 row # LSB Gray code
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ECE 331 - Digital System Design 5 x 1 x 2 x 3 x 4 00 01 11 10 00 01 11 10 x 2 x 4 x 1 m 0 m 1 m 5 m 4 m 12 m 13 m 8 m 9 m 3 m 2 m 6 m 7 m 15 m 14 m 11 m 10 Four-variable K-Map Gray code Gray code
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ECE 331 - Digital System Design 6 Minimization using K-Maps
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ECE 331 - Digital System Design 7 Minimization using K-maps Enter minterms (for SOP) into K-map Identify adjacent cells Minterms differ in only one bit Use adjacency to minimize logic function Gray code used for enumeration Specifies the location of each minterm in K-map Horizontal and Vertical adjacency Both are logically adjacent K-map wraps Left and right columns are logically adjacent Top and bottom rows are logically adjacent
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ECE 331 - Digital System Design 8 Minimization using K-Maps Group adjacent cells to reduce functional expression Adjacencies are of size 1, 2, 4, 8, … - Number of adjacent cells is a power of 2 - Adjacent cells form a rectangle The larger the grouping of adjacent cells the greater the minimization of the logical function.
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Lecture_7 - ECE 331 Digital System Design Karnaugh Maps and...

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