Lab2 - Score Date Name_Partner TA Signoff Grades ECE 3055A...

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Score:_____ Date:____ Name:__________________Partner:_________________ ECE 3055A Lab Assignment #2 - Counts as two labs Part 1(25%)_______________________ Part 2 (75%)___________________________ Due Date Part 1: Thursday, September 30 Due Date Part 2: Thursday, October 14 Note: This assignment has two parts, the first part is simple, you just have to run an existing VHDL-based MIPS hardware simulation using the new Altera Quartus II CAD tools and understand the results. The second part, adding Pipelining to the model will take a significant effort , so be sure to start work early to be able to finish on time. The Altera Quartus II tools are available in the ECE PC labs or on the web using the link at The MIPS VHDL source files are also available on a link on the class web page at: Note: Get the new files for this Semester from this location only! – see the separate handout passed out earlier on how to run the new MIPS model using Quartus II. Avoid using Quartus versions newer than the ones you used in 2031 lab, in the newest one 10.0 a different simulator is used that is a bit more complex. Older ones are posted at Altera. 1. Use VHDL to synthesize the MIPS single clock cycle design in the top-level file MIPS.VHD. More information on this model can be found in the last chapter of your ECE 2031 textbook. An earlier chapter also contains a review of VHDL. After synthesis and simulation perform the following steps: Display and print the timing diagram from the simulation. Verify that the information on the timing diagram shows that the hardware is functioning correctly. Examine the test program in PROGRAM.MIF . Look at the program counter, instruction bus, register file, ALU outputs, and control signals on the timing diagram and carefully follow the execution of each instruction in the test program. Label the important values for each instruction on the timing diagram and attach a short write-up explaining in detail what the timing diagram shows relative to each instruction's execution and correct operation. Return to the simulator and run the simulation again. Examine the ALU output in the timing diagram window. Zoom in on the ALU output after execution of the third instruction and see what happens when it changes values. Explain exactly what is happening at this point. Hint: Real hardware like adders have timing delays. 2. Pipeline the MIPS VHDL simulation. Test your VHDL model by running a simulation of the example program using the hardware shown in Computer Organization and Design The Hardware/Software Interface. This detailed example is from the earlier third edition of the text, so the figures are attached at the end of this handout. To minimize changes,
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pipeline registers must be placed in the VHDL module that generates the input to the pipeline. As an example, all of the pipeline registers that store control signals must be placed in the control module. Synthesize and check the control module first, since it is
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Lab2 - Score Date Name_Partner TA Signoff Grades ECE 3055A...

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