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lab3 - Score Date Name_Partner ECE 3055 Laboratory...

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Score:_____ Date:______ Name:___________________________Partner:________________________ ECE 3055 Laboratory Assignment 3 Due Date Part I: November 2, Due Date Part II: November 9 Part 1(75%)_______________________ Part 2 (25%)___________________________ Part I: Clock Rate & Forwarding Compare the maximum clock rate on the original non-pipelined design to the new clock rate on your pipeline solution from the previous lab. Open the project and use Quartus to calculate it with Processing -> Classic Timing Analyzer Tool . Be prepared to explain these results to the TA. Max Clock frequency _________ Max Clock frequency with pipeline = _________ Once the MIPS is pipelined as in Lab 2, data hazards can occur between the five instructions present in the pipeline. As an example, consider the following program: Sub $2,$1,$3 Add $4,$2,$5 The subtract instruction stores a result in register 2 and the following add instruction uses register 2 as a source operand. The new value of register 2 is written into the register file by SUB $2,$1,$3 in the write-back stage after the old value of register 2 was read out by ADD $4,$2,$5 in the decode stage. In the text, this problem is fixed by adding two forwarding muxes to each ALU input in the execute stage. In addition to the existing values feeding in the two ALU inputs, the forwarding multiplexers can also select the last ALU result or the last value in the data memory stage. These muxes are controlled by comparing the rd, rt, and rs register address fields of instructions in the decode, execute, or data memory stages. Instruction rd fields will need to be added to the
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