homework_lec1-lec14_

homework_lec1-lec14_ - Lec 1- overview of microelectronic...

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Unformatted text preview: Lec 1- overview of microelectronic fabrication 1. A simple pn junction diode is shown in cross section in the following Fig. Make a possible process flowchart for fabrication of this structure, including mask steps. Problem 1. Solutions: 2. Draw a set of contact and metal masks for the bipolar transistor of above Figure. Use square contact windows with one contact to the emitter and two contacts to the base and collector regions. Solutions: Assume negative photoresist is used. mask 3 Thermal Oxidation mask 1 N+ window definition (photolithography) Phosphorous diffusion & oxidation Metal deposition Metal lithography Contact opening definition (photolithography) mask 2 N+ window etch Contact etch Metallization etch Problem 1. Problem 2. Generated by Foxit PDF Creator © Foxit Software http://www.foxitsoftware.com For evaluation only. 3. According to the process steps of Al-gate NMOS and PolySi-gate Self-Aligned NMOS, give reasons why the ladder substitutes the former. Solutions: We can resolve this problem in four aspects: First of all, from the above layouts of Al-gate and PolySi-gate NMOS, we see that the width of PolySi determines the channel length in PolySi-gate NMOS, which is only determined by the resolution of photolithography & etching. While in Al-gate NMOS, the channel length is determined by gate oxide. In order to avoid lithography misalignment between gate oxide and S/D region, we must reserve some area---overlap of gate mask over S/D active region mask, which will not only introduce area waste but also generate gate-source and gate-drain parasitic overlap capacitance. So, the most important advantage of PolySi-gate technology over metal-gate technology is layout & parasitic capacitance reduction . In addition, Polysi-gate can withstand high temperature processing , which is the main reason to implement self-aligned S/D implant. And PolySi gate can be directly oxidized at high temperature to form an insulating layer over the gate . For this reason, heavily doped polysi represents an additional interconnect layer that other metal layers can easily cross , because of the oxide isolation. Besides, Phosphorous doped PolySi can reduce mobile ionic contamination, which gives better threshold control . Generated by Foxit PDF Creator © Foxit Software http://www.foxitsoftware.com For evaluation only. Lec 2-Crystal Growth and wafering Problem: Please summarize the effects of Si wafer orientation on IC. Solution: • The basic electrical and mechanical properties of the wafer depend on wafer orientation, impurity type and concentration. • ICs are made on low crystal plane index substrate. Usually, MOS ICs use {100} wafer and bipolar ICs use {111} wafer....
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This note was uploaded on 01/24/2011 for the course ECE 538 taught by Professor Ozturk during the Fall '09 term at N.C. State.

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homework_lec1-lec14_ - Lec 1- overview of microelectronic...

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