hw5-09 - 1 Fundamentals of Digital System Design ECE/CS...

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1 Fundamentals of Digital System Design ECE/CS 3700 Spring 2009, Homework # 5 Due Date: Wed, April 29 by 5pm in the HW locker. 1. (15 points) Generalized Counter Design: Interpreting counters as finite state machines . You are asked to design a “synchronous” 3-bit counter that advances through the sequence: 000, 010, 011, 101, 110, 000, and repeats. Not all possible combinations of the 3 bits represent valid (or legal, or care) states of the counter. The unused (illegal, or don’t care) states are 001, 100, 111. These states can be used as don’t care conditions to simplify the logic used to implement the counter. The state transition table of the above counter is shown below, where a, b, c represent present state values and a + , b + , c + , represent next state values in the latches. d denotes don’t cares in the next state columns. TABLE I STATE TRANSITION TABLE OF THE COUNTER Present State Next State abc a + b + c + 0 0 0 0 1 0 0 0 1 d d d 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 d d d 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 d d d Express each next-state bit as a combinational logic function of the three present-state bits. Use the don’t cares to minimize the functions. Implement the counter using
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This note was uploaded on 01/24/2011 for the course ENGR 3700 taught by Professor Kal during the Spring '10 term at Utah State University.

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hw5-09 - 1 Fundamentals of Digital System Design ECE/CS...

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