CA5.5 - 1 Chapter 5 (cont.) The Processor: DataPath and...

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Unformatted text preview: 1 Chapter 5 (cont.) The Processor: DataPath and Control 2 Given Datapath: RTL -> Given Datapath: RTL -> Control Control ALUctr RegDst ALUSrc ExtOp MemtoReg MemWr Zero Instruction<31:0> <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rs Rt nPC_sel Adr Inst Memory DATA PATH Control Op <21:25> Fun RegWr 3 Putting it All Together: A Single Cycle Putting it All Together: A Single Cycle Datapath Datapath imm16 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction<31:0> 1 1 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rt Rs = Adder Adder PC Clk 00 Mux 4 nPC_sel PC Ext Adr Inst Memory 4 Putting it All Together: A Single Cycle Putting it All Together: A Single Cycle Datapath Datapath imm16 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction<31:0> 1 1 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rt Rs = Adder Adder PC Clk 00 Mux 4 nPC_sel PC Ext Adr Inst Memory 5 Putting it All Together: A Single Cycle Putting it All Together: A Single Cycle Datapath Datapath imm16 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction<31:0> 1 1 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rt Rs = Adder Adder PC Clk 00 Mux 4 nPC_sel PC Ext Adr Inst Memory 6 Putting it All Together: A Single Cycle Putting it All Together: A Single Cycle Datapath Datapath imm16 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction<31:0> 1 1 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rt Rs = Adder Adder PC Clk 00 Mux 4 nPC_sel PC Ext Adr Inst Memory 7 Putting it All Together: A Single Cycle Putting it All Together: A Single Cycle Datapath Datapath imm16 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction<31:0> 1 1 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rt Rs = Adder Adder PC Clk 00 Mux 4 nPC_sel PC Ext Adr Inst Memory 8 Putting it All Together: A Single Cycle Putting it All Together: A Single Cycle Datapath Datapath imm16 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction<31:0> 1 1 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rt Rs = Adder Adder PC Clk 00 Mux 4 nPC_sel PC Ext Adr Inst Memory 9...
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CA5.5 - 1 Chapter 5 (cont.) The Processor: DataPath and...

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