CA5 - Chapter 5 The Processor: DataPath and Control 1 The...

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Unformatted text preview: Chapter 5 The Processor: DataPath and Control 1 The Big Picture: Where are We The Five Classic Components of a • Now? Computer 5 6 Processor Processor Control Memory Datapath Output 7 Input 8 • Today’s Topic: Design a Single Cycle 2 The Performance • Performance of a machine is determined by: Perspective • • – Instruction count – Clock cycle time – CPI Processor design (datapath and control) will determine: – Clock cycle time – Clock cycles per instruction Today: – Single cycle processor: • Advantage: One clock cycle per instruction • Disadvantage: long cycle time 3 How to Design a Processor: step­by­ 1. Analyze instruction set => datapath requirements • step – the meaning of each instruction is given by the register transfers – datapath must include storage element for ISA registers – datapath must support each register transfer • 2. Select set of datapath components and establish • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to • 5. Assemble the control logic clocking methodology determine setting of control points that effects the register transfer. 4 The MIPS Instruction Formats • All MIPS instructions are 32 bits long. The three instruction formats: – R­type – I­type – J­type 31 op 6 bits 31 op 6 bits 31 op 6 bits 26 target address 26 bits 26 rs 5 bits 26 rs 5 bits 21 rt 5 bits 21 rt 5 bits 16 immediate 16 bits 0 16 rd 5 bits 11 shamt 5 bits 6 funct 6 bits 0 0 5 • ADD and SUB • • • Step 1a: The MIPS Subset for today 31 26 op 6 bits 26 op 6 bits 26 op 6 bits 26 op 6 bits 26 target address 26 bits 6 21 rs 5 bits 21 rs 5 bits 21 rs 5 bits 21 rs 5 bits 16 rt 5 bits 16 rt 5 bits 16 rt 5 bits 16 rt 5 bits 11 rd 5 bits shamt 5 bits 6 funct 6 bits 0 • Jump – addU rd, rs, rt – subU rd, rs, rt 31 OR Immediate: – ori rt, rs, imm16 31 LOAD and STORE – lw rt, rs, imm16 – sw rt, rs, imm16 31 BRANCH: – beq rs, rt, imm16 31 0 immediate 16 bits immediate 16 bits 0 immediate 16 bits 0 0 – J imm26 op 6 bits Logical Register Transfers • RTL gives the meaning of the instructions op | rs | rt | rd | shamt | funct = MEM[ PC ] • All start by fetching the instruction inst ADDU SUBU ORi LOAD STORE BEQ Register Transfers R[rd] <– R[rs] + R[rt]; R[rd] <– R[rs] – R[rt]; R[rt] <– R[rs] | zero_ext(Imm16); PC <– PC + 4 PC <– PC + 4 PC <– PC + 4 PC <– PC + 4 PC <– PC + 4 op | rs | rt | Imm16 = MEM[ PC ] R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; if ( R[rs] == R[rt] ) then PC <– PC + 4 sign_ext(Imm16)] || 00 else PC <– PC + 4 7 • Memory Step 1: Requirements of the Instruction Set – instruction & data • Registers (32 x 32) – read RS and RT – Write RT or RD • PC • Extender • Add and Sub register or extended immediate • Add 4 or extended immediate to PC 8 Step 2: Components of the Datapath • Combinational Elements • Storage Elements – Clocking methodology 9 Combinational Logic Elements (Basic Building CarryIn Blocks) • Adder • MUX • ALU A B 32 32 Select Adder 32 Sum Carry A B 32 32 OP A B 32 32 MUX ALU 32 Y 32 Result 10 10 • Storage Element: Register (Basic Building Block) Register Similar to the D Flip Flop except Write Enable – • N­bit input and output Data In Data Out N N • Write Enable input – Write Enable: Clk • negated (0): Data Out will not change • asserted (1): Data Out will become Data In 11 11 Storage Element: Register File • Register File consists of 32 registers: EnableRW RA RB Write 5 5 5 • • – Two 32­bit output busses: busA busA and busB busW 32 32 32-bit 32 Registers busB – One 32­bit input bus: busW Clk 32 Register is selected by: – RA (number) selects the register to put on busA – RB (number) selects the register to put on busB – RW (number) selects the register to be written via busW when Write Enable is 1 Clock input (CLK) – The CLK input is a factor ONLY during write – During read, behaves as a combinational logic: • RA or RB valid => busA or busB valid after 12 12 “access time.” • Memory (idealized) • Storage Element: Idealized Write Enable Memory Address • Data In DataOut – One input bus: Data In 32 32 – One output bus: Data Out Clk Memory word is selected by: – Address selects the word to put on Data Out – Write Enable = 1: address selects the memory word to be written via the Data In bus Clock input (CLK) – The CLK input is a factor ONLY during write operation – During read operation, behaves as a combinational logic block: • Address valid => Data Out valid after “access 13 13 Clk Clocking Methodology Setup Hold . . . . . . Setup Hold Don’t Care . . . . . . • All storage elements are clocked by the same • • clock edge Cycle Time = CLK­to­Q + Longest Delay Path + Setup + Clock Skew (CLK­to­Q + Shortest Delay Path ­ Clock Skew) > 14 14 Step 3: Assemble DataPath meeting requirements • Register Transfer Requirements ⇒ Datapath Assembly • Instruction Fetch • Read Operands and Execute Operation 15 15 3a: Overview of the Instruction Fetch Unit • The common RTL operations – Fetch the Instruction: mem[PC] – Update the program counter: • Sequential Code: PC <­ PC + 4 • Branch and Jump: PC <­ “something else” Clk PC Next Address Logic Address Instruction Memory Instruction Word 32 16 16 3b: Add & Subtract • R[rd] <­ R[rs] op R[rt] instruction RegWr Rd Rs Rt 55 5 Rw Ra Rb busW 32 Clk 32 32-bit Registers busA 32 busB 32 Result 32 ALU – Ra, Rb, and Rw come from inst’s rs, rt, & rd – ALUctr and RegWr: control logic after decoding the ALUctr 17 17 Clk PC Register­Register Timing: One complete cycle Old Value Clk-to-Q New Value Old Value Old Value Old Value Old Value Old Value Instruction Memory Access Time New Value Delay through Control Logic New Value New Value Register File Access Time New Value ALU Delay New Value Rs, Rt, Rd, Op, Func ALUctr RegWr busA, B busW Rd Rs Rt RegWr 5 5 5 busW 32 Clk Rw Ra Rb 32 32-bit Registers busA 32 busB 32 ALUctr Register Write Occurs Here Result 32 ALU 18 18 • R[rt] <­ R[rs] op ZeroExt[imm16] ] 16 31 26 21 op 6 bits 31 0000000000000000 16 bits Rt Rs Rt? 5 5 busA 32 busB 32 ZeroExt 32 ALUSrc rs 5 bits rt 5 bits 3c: Logical Operations with Immediate 11 immediate 16 bits rd? immediate 16 bits 0 16 15 0 RegDst Rd Mux RegWr 5 busW 32 Clk ALUctr Rw Ra Rb 32 32-bit Registers Result 32 ALU Mux imm16 16 19 19 3d: Load rt] <­ Mem[R[rs] + SignExt[imm16]] • R[Operations lw rt, rs, imm16 31 Rd RegDst Mux RegWr 5 busW 32 Clk Rt 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 11 Example: 0 immediate 16 bits rd Rs Rt? 5 5 busA 32 busB 32 Extender 32 ALUctr W_Src ALU 32 MemWr WrEn Adr Data Memory 32 Rw Ra Rb 32 32-bit Registers Mux Mux ?? ALUSrc Data In 32 Clk imm16 16 ExtOp 20 20 3e: Store Operations • Mem[ R[rs] + SignExt[imm16] <­ R[rt] ] sw rt, rs, imm16 31 26 op 6 bits Rd Rt RegDst Mux RegWr 5 busW 32 Clk 5 Rs 5 Rt busA 32 busB 32 Extender 32 Mux ALU 32 21 rs 5 bits 16 rt 5 bits immediate 16 bits ALUctr MemWr Example: 0 W_Src Rw Ra Rb 32 32-bit Registers Mux imm16 Data In 32 Clk ALUSrc WrEn Adr Data Memory 32 16 ExtOp 21 21 3f: The Branch Instruction 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits immediate 16 bits 0 • beq rs, rt, imm16 Fetch the instruction from memory – mem[PC] Calculate thebranch – Equal <­ R[rs] == R[rt] condition Calculate the next instruction’s address – if (Equal) • PC <­ PC + 4 + ( SignExt(imm16) x 4 ) – else • PC <­ PC + 4 22 22 Datapath for Branch Operations • beq rs, rt, imm16 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits Datapath generates condition (equal) 0 immediate 16 bits Cond Rs Rt busA 32 busB 32 Equal? Inst Address 4 Adder Mux Adder PC Ext nPC_sel 32 00 busW Clk RegWr 5 5 5 Rw Ra Rb 32 32-bit Registers PC imm16 Clk 23 23 Putting it All Together: A Single Cycle Instruction<31:0> Datapath Inst Memory <21:25> <16:20> <11:15> <0:15> Adr Rs nPC_sel RegDst Rt Rd Imm16 Equal Rs Rt = ALU 0 Mux 32 WrEn Adr Data Memory 0 Mux ALUctr MemWr MemtoReg Rd Rt 1 0 5 5 4 00 Adder Mux Adder PC Ext RegWr 5 busW 32 Clk Clk imm16 busA Rw Ra Rb 32 32-bit Registers busB 32 Extender 32 PC 1 32 32 Data In Clk 1 imm16 16 ExtOp ALUSrc 24 24 An Abstract View of the Critical • Register file and ideal memory: Path – The CLK input is a factor ONLY during write operation – During read operation, behave as combinational logic: • Address valid => Output valid after “access time.” Ideal Instruction Memory Instruction Address Instruction Rd Rs 5 5 Rt 5 Imm 16 A 32 PC Rw Ra Rb 32 32-bit Registers 32 B Critical Path (Load Operation) = PC’s Clk-to-Q + I- Memory’s Access Time + Reg File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Reg File Write + Clock Skew Data 32 Address Ideal Data Data In Memory ALU Clk Next Address Clk Clk 32 25 25 An Abstract View of the Implementation Ideal Instruction Memory Instruction Address Next Address 32 PC Control Instruction Rd Rs 5 5 Rt 5 A Rw Ra Rb 32 32-bit Registers 32 B ALU 32 Data Address Data In Clk Data Out Control Signals Conditions Ideal Data Memory Clk Clk 32 Datapath 26 26 Summar y • 5 steps to design a processor – 1. Analyze instruction set => datapath requirements – 2. Select set of datapath components & establish clock methodology – 3. Assemble datapath meeting the requirements – 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. – 5. Assemble the control logic 27 27 Summary (cont.) • MIPS makes it easier – Instructions same size – Source registers always in same place – Immediates same size, location – Operations always on registers/immediates • Single cycle datapath => CPI=1, CCT => long • Next time: implementing control 28 28 ...
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