CA73 - Chapter 7 Cache Reloaded 1 Last Time: Fully...

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1 Chapter 7 Cache Reloaded
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Last Time: Fully Associative Cache 31 5 4 0 Cache Tag (27 bits) Byte Select Valid Bit Cache Data Holds 4 blocks Byte 31 ... Byte 1 Byte 0 Byte 31 ... Byte 1 Byte 0 = = = = Hit Return bytes of “hit” cache line Block # (”Tags”) 26 0
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Last Time: Fully Associative Cache 31 5 4 0 Cache Tag (27 bits) Byte Select = = = = Hit Block # (”Tags”) 26 0 1) Expensive comparators tag space 2) Slow – may affect clock rate 3) Not scalable 4) High power consumption Ideal, but …
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Building a cache with one comparators 32-byte blocks Block # 0 1 2 3 4 5 Blocks of a certain color may only appear in one line of the cache. 32-bit Memory Address 31 7 6 5 4 0 Which block? C o l o r Byte # 25 bits 2 bits 5 bits Cache index
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Example: A Direct Mapped Cache Cache Tag (25 bits) Index Byte Select 5 31 0 4 Ex: 0x01 Ex: 0x00 Return bytes of “hit” cache line PowerPC 970: 64K direct- mapped Level-1 I-cache 6 7 Valid Bit Byte 31 ... Byte 1 Byte 0 Byte 31 ... Byte 1 Byte 0 Cache Tags 0 24 Cache Data
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A Direct-Mapped Cache 32-byte blocks Block # 0 1 2 3 4 5 It works fine if blocks of different colors are referenced. example: 0 1 2 3 If the cache has 4 lines, we will see ~100% hit rate. Cache
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Shortcomings of direct-mapped caches 32-byte blocks Block # 0 1 2 3 4 5 Cache But what if …. example: 2 6 10 14 If the cache has 4 lines, we will see ~0% hit rate, since all blocks are competing for the red line.
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Hybrid Design: Set Associative Cache Cache Tag (26 bits) Index Byte Select (4 bits) PowerPC 970: 32K 2-way set associative L1 D-cache Valid Cache Block Cache Block Cache Tags Cache Data Cache Block Cache Block Cache Tags Valid Cache Data Ex: 0x01 Hit Right Return bytes of “hit” set member “N-way” set associative -- N is number of blocks for each color 16 bytes 16 bytes
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Exercise Assume we have a 16KB cache, with 32B cache lines, and 32-bit address. Q1: How many lines do we have? 512 Q2: How many comparators are needed for a fully associative cache? 512 Q3: How many bits are used for tag in a direct mapped cache ? 18 Q4: How many bits are used to select a set in the 4-way associative cache? 7
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Another Exercise Assume we have a 64KB cache, with 64B cache lines. Q1: How many lines do we have? 1024 Q2: How many sets do we have for a fully associative cache? 1 Q3: How many bits are used for tag in a 4-way associative cache ? 18 Q4: How many sets do we have for a 8-way associative cache? 128
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Set Associative Caches Cache Tag (T) Set Select (S) Byte Select (B) 31 0 B : Number of bits determined by the line size, e.g. if line size=32B, B=5 S : Number of bits determined by the number of sets, e.g. if there are 1024 sets, S=10 T : Number of bits used for Tag. T=32-B-S. For 64-bit architectures, T=64-B-S
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Set Associative Caches Cache Tag (T) Set Select (S) Byte Select (B) 31 0 Example : Assume cache size=32KB, line size=32B. 1) Direct-mapped cache:
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This note was uploaded on 01/26/2011 for the course CSCI 4203 taught by Professor Weichunghsu during the Fall '05 term at Minnesota.

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CA73 - Chapter 7 Cache Reloaded 1 Last Time: Fully...

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