vlog - Verilog Tutorial csci4203/ece4363 csci4203/ece4363 1...

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Unformatted text preview: Verilog Tutorial csci4203/ece4363 csci4203/ece4363 1 How to use Verilog on Itlab machines • • • • • • module load ecad/modeltech add to your .login or .cshrc file Creat a work directoy: % vlib work Generate verilog code use sample code as a base, e.g. mult3.v Compile the design (e.g., mult4.v) % vlog mult4.v Check compile messages, make sure no compilation failures Compile testbench (e.g., tb7.v) % vlog tb7.v Simulate the design % vsim ­c tb7 VSIM 1> run Check simulation results. csci4203/ece4363 csci4203/ece4363 VSIM 2> quit What is Verilog • • • • • • Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It can be used to describe a LANGUAGE digital system. digital Originally developed by Gateway Design Originally Automation in 1984 Automation Cadence Design System acquired Gateway and Cadence became the owner of Verilog in 1990. became In 1991, Cadence organized OVI (Open Verilog International) to open the language. (otherwise, VHDL would have won). VHDL In 1995, Verilog became IEEE standard Commonly used verilog tools: Verilog-XL, VCS simulator csci4203/ece4363 csci4203/ece4363 Hierarchical Design Flow Digital System A MIPS processor Abstraction Gap Billions of transistors csci4203/ece4363 csci4203/ece4363 Hierarchical Design Flow Digital System ISA Functional Description Register Transfer level A MIPS processor Automatic Synthesis using compiler Structural Level Physical Level Billions of transistors csci4203/ece4363 csci4203/ece4363 Why Verilog for this class • Verilog is C-like, easy for EE/CS students to Verilog • • • • • learn learn It is widely used It is IEEE standard Learning Verilog provides an easy path to Learning learning any other HDL learning Many efficient simulators available Conform to other courses csci4203/ece4363 csci4203/ece4363 A Full Adder a b Carry out Carry in sum csci4203/ece4363 csci4203/ece4363 Verilog Module of a Full Adder a b Sum = a ^ b ^ Cin; Carry­out = a&b + a&Cin + b&Cin Carry out sum Carry in csci4203/ece4363 csci4203/ece4363 Verilog Module of a Full Adder a b Sum = a ^ b ^ Cin; Carry­out = a&b + a&Cin + b&Cin Carry out sum Carry in module full_adder(a,b,cin,s,cout); input a,b,cin; output s,cout; assign s=a ^ b ^ cin; assign cout=(a&b) | (a&cin) | (b&cin); endmodule csci4203/ece4363 csci4203/ece4363 A 4­bit Ripple­Carry Adder a3 b3 a2 b2 a1 b1 a0 b0 Cout Cin Cin Cin Cin sum4 sum3 sum2 sum1 sum0 csci4203/ece4363 csci4203/ece4363 A 4­bit Ripple­Carry Adder Module RCA(a,b,ci,s) input [3:0] a,b; input ci; output [4:0] s; wire [2:0] carry; full_adder fa0(a[0], b[0], ci, s[0], carry[0]); full_adder fa1(a[1], b[1], carry[0], s[1], carry[1]); full_adder fa2(a[2], b[2], carry[1], s[2], carry[2]); full_adder fa3(a[3], b[3], carry[2], s[3], s[4] ); endmodule csci4203/ece4363 csci4203/ece4363 Instantiate 4 copies of full_adders Declarations • • • Ports define the connection to external world. They can be type input, output, or inout. e.g. input [3:0] a,b; Internal net variables which connect multiple elements are often declared using keyword wire within the module. e.g. wire [2:0] carry; Register variables correspond to elements with memory that can store value until they are next updated. e.g. reg a; csci4203/ece4363 csci4203/ece4363 Vector and Arrays • For groups of nets or registers. e.g. a bus or a register e.g. a 8­bit bus can be defined as wire [7:0] address; or wire [0:7] address; Vector of vector e.g. reg [7:0] cache [511:0]; this defines an array of 512 reg variables, each of which is an 8­bit wide vector. Verilog does csci4203/ece4363 csci4203/ece4363 • A 3­bit X 3­bit Unsigned Multiplier a2 a2 a2 a1 a1 a0 a1 a0 a0 b0 b1 b2 P5 P4 P3 P2 P1 P0 csci4203/ece4363 csci4203/ece4363 =a1&b0 ^ a0&b1 =a0&b0 and carry 14 // half adder component used in the multiplier module half_adder(a, b, s, cout); input a, b; output s, cout; assign s = a^b; assign cout = a&b; endmodule // full adder component used in the multiplier module full_adder(a, b, cin, s, cout); input a, b, cin; output s, cout; assign s = a^b^cin; assign cout = (a&b) | (b&cin) | (a&cin); endmodule csci4203/ece4363 csci4203/ece4363 15 Half adder and Full Adder // 3­bit by 3­bit unsigned multiplier module mult3(x, y, p); input [2:0] x, y; output [5:0] p; wire t1, t2, t3, t4, t5, t6, t7; // structural description assign p[0] = x[0]&y[0]; half_adder ha1(x[1]&y[0], x[0]&y[1], p[1], t1); half_adder ha2(x[2]&y[0], x[1]&y[1], t2, t3); full_adder fa1(t2, t1, x[0]&y[2], p[2], t4); full_adder fa2(x[2]&y[1], t3, x[1]&y[2], t5, t6); half_adder ha3(t5, t4, p[3], t7); full_adder fa3(x[2]&y[2], t6, t7, p[4], p[5]); endmodule csci4203/ece4363 csci4203/ece4363 16 ...
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  • Fall '05
  • WeiChungHsu
  • Electronic design automation, SystemC, Full  Adder, 4­bit Ripple­Carry Adder, Generate verilog code

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