vlog_behavior

vlog_behavior - Verilog Tutorial (Behavioral Models)...

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Unformatted text preview: Verilog Tutorial (Behavioral Models) 11/15/2005 Changho Choi choi@cs.umn.edu csci4203/ece4363 csci4203/ece4363 1 Agenda • How to use Vespa simulator in itlab machines • Behavioral and structural models – Example (3x3 unsigned multiplier) • Algorithmic Behavioral model (behavior.v) • Questions? csci4203/ece4363 csci4203/ece4363 2 How to use Vespa Simulator (with demo) • • • – download updated_vespa.tar file untar updated_vespa.tar file %tar xvf updated_vespa.tar compile vespa compiler % cd updated_vespa/vasm % make • • ignore a warning message misc.c: In function 'err_exit': misc.c:15: warning: incompatible implicit declaration of built­in function 'exit‘ Or you might want to add “#include <stdlib.h>” line • – – prepare hexa code for simulation Generate a testbench program tb_shiftMult.asm file in the current directory % vi tb_shiftMult.asm compile tb_shiftMult.asm file and v.out file will be generated csci4203/ece4363 csci4203/ece4363 tb_shiftMult.asm LDI r0, #64782 SLL r1, r0, #24 SRL r2, r1, #18 LDI r3, #5326 MULU r4, r2, r3 HLT Final Results: (testbench assembly program) // r0 = 0000 FD0E // r1 = 0E00 0000 // r2 = 0000 0380 (896) // r3 = 0000 14CE // r4 = 0048 d100 (4,772,096) . . . . . . # Instruction #: 6 PC=00000018 OPCODE=31 IR=f8000000 # Condition codes: C=0 V=0 Z=0 N=0 # R[ 0]: 0000fd0e 0e000000 00000380 000014ce # R[ 4]: 0048d100 xxxxxxxx xxxxxxxx xxxxxxxx # R[ 8]: xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx csci4203/ece4363 csci4203/ece4363 4 How to use Vespa Simulator(Cont’d) • Prepare Vespa simulator % cd ../behavioral % vlib work % vlog behavioral.v Now it is ready to run Vespa simulator. run Vespa code copy v.out hex file in the current directory % cp ../vasm/v.out . run Vespa simulator % vsim ­c vespa run ­all • – – • Compare the results of a testbench program to the expected register values csci4203/ece4363 csci4203/ece4363 Questions for Vespa Simulator? csci4203/ece4363 csci4203/ece4363 6 Hierarchical Design Flow Digital System A MIPS processor Abstraction Gap Billions of transistors csci4203/ece4363 csci4203/ece4363 Hierarchical Design Flow Digital System ISA Functional Description Register Transfer level Structural Level Physical Level A MIPS processor Billions of transistors csci4203/ece4363 csci4203/ece4363 Hierarchical Design Flow Digital System ISA Functional Description Register Transfer level Structural Level A MIPS processor Behavioral model Structural model Physical Level Billions of transistors csci4203/ece4363 csci4203/ece4363 Behavioral and Structural models • Behavioral model – Coarsely described design at high level of abstraction – Details of precise implementation are hidden – Looks like high­level language (e.g., c) • if, for, and case statements – Lower level of implementation – Design in gate or block level – Hierarchical interconnection of sub modules • Mult3 ­ half/full adder csci4203/ece4363 csci4203/ece4363 10 • Structural model A 3­bit X 3­bit Unsigned Multiplier a2 a2 a2 a1 a1 a0 a1 a0 a0 b0 b1 b2 P5 P4 P3 P2 P1 P0=a0&b0 csci4203/ece4363 csci4203/ece4363 =(a1&b0 ^ a0&b1) and carry 11 Structural model (3x3 unsigned multiplier) module mult3_strutural(x, y, p); input [2:0] x, y; output [5:0] p; wire t1, t2, t3, t4, t5, t6, t7; // structural description assign p[0] = x[0]&y[0]; half_adder ha1(x[1]&y[0], x[0]&y[1], p[1], t1); half_adder ha2(x[2]&y[0], x[1]&y[1], t2, t3); full_adder fa1(t2, t1, x[0]&y[2], p[2], t4); full_adder fa2(x[2]&y[1], t3, x[1]&y[2], t5, t6); half_adder ha3(t5, t4, p[3], t7); full_adder fa3(x[2]&y[2], t6, t7, p[4], p[5]); endmodule csci4203/ece4363 csci4203/ece4363 12 Behavioral model (3x3 unsigned multiplier) module mult3_behavioral; reg [2:0] x, y; reg [5:0] result; reg [5:0] p; integer i; initial begin x = 5; y=7; result = 0; for(i=0;i<3;i=i+1) if(y[i] == 1'b1) result = result + (x<< i); p = result[5:0]; end endmodule $display("%d*%d = %d", x, y, p) ; csci4203/ece4363 csci4203/ece4363 13 Questions for Behavioral and Structural Models? csci4203/ece4363 csci4203/ece4363 14 Vespa Behavioral.v architecture module vespa; // start of vespa processor module // 1. Declare global parameter // 2. Register declaration // ­ Declare storage element in ISA (instruction set architecture) // ­ Declare internal registers for ALU operations // 3. Instruction field and opcode definition // 4. Main fetch­execute loop // 5. Task and function definitions // 6. Utility operations and functions (e.g., condition code) endmodule // end of vespa processor module csci4203/ece4363 csci4203/ece4363 15 1. Declare global parameters • Assign a symbolic name to a constant • Use that name to refer the value parameter parameter parameter WIDTH = 32; // Datapath width NUMREGS = 32; // Number of registers in the ISA. MEMSIZE = (1<<13); // Size of the memory actually // simulated. Address range is // 0 to (2^13 ­ 1). . . . . . . reg [WIDTH­1:0] PC; csci4203/ece4363 csci4203/ece4363 16 2. Register delcaration • Declare all of the storage elements for ISA and ALU operations • Basic Verilog storage element is a single bit register (reg: e.g., C, Z) • Vector of bits for multibit registers (e.g., PC, OP1) reg C; // condition code bit reg Z; // condition code bit . . . . . . reg [WIDTH­1:0] PC; // program counter . . . . . . reg [WIDTH­1:0] op1; // Source operation 1 csci4203/ece4363 csci4203/ece4363 17 3. Instruction field and opcode definition • Define easy­to­read name for each opcode using `define macro statement • Textual substitution of name to value occurs whenever a compiler encounters the name (e.g., ADD ­> ‘d1) `define NOP ‘d0 `define ADD ‘d1 `define SUB ‘d2 . . . . . . `define HLT ‘d31 . . . . . . `define OPCODE IR[31:27] // opcode field `define rdst IR[26:22] // detinstion register csci4203/ece4363 csci4203/ece4363 `define rs1 IR[21:17] // source register 1 ‘d: decimal ‘h: hexadecimal ‘b: binary ‘o: octal 18 Parameter and `define macro • Both parameter and define macro can be used to define • constants Parameter – – – Parameter WIDTH=32; A constant that is local to module Can optionally be redefined • Define macro – Referenced the parameter name – `define ADD ‘d1 – Global from the point of definition and remain active until aonther macro definition changes the value or “undef” is met – Generally will not modified elsewhere in the design – Referenced through ‘name (e.g., ‘ADD) csci4203/ece4363 csci4203/ece4363 19 • #(parameter WIDTH=16) 4. Fetch­Execute Loop memory and store in the IR • Fetch the next instruction to be executed from • Decode and perform the fetched instruction Initial begin $readmemh(“v.out”, MEM); // read v.out file into MEM RUN = 1; PC = 0; while(RUN==1) begin fetch; // user defined tasks execute; // like procedure call print_trace; end . . . $finish ; // system defined task end csci4203/ece4363 csci4203/ece4363 v. out @0000 58 00 78 e4 @0004 78 40 80 00 @0008 58 80 cd 92 @000c 18 c2 10 00 @0010 58 00 5c 3b @0014 78 40 80 00 @0018 58 80 46 af 20 – PC (Program Counter) points the next instruction 5. Fetch task • • Read the value in memory currently pointed by the PC and store that value to the IR The read instruction will be the next instruction to be executed task fetch; begin IR = read_mem(PC) ; // function to read 32­bit word PC = PC + 4; // PC points to the next instruction to be executed end endtask csci4203/ece4363 csci4203/ece4363 21 Function – – – – • Function is similar to a task except that it Requires at least one input Returns exactly one value Is not allowed to call other tasks Can not contain any delays • Function call – statement = < function name > ( arguments to be passed ); • read_mem function • IR = read_mem(PC); – Read a 32­bit word from memory starting at the address given. function [WIDTH­1:0] read_mem; input [WIDTH­1:0] addr; // the address from which to read read_mem = {MEM[addr],MEM[addr+1],MEM[addr+2],MEM[addr+3]}; endfunction // read_mem csci4203/ece4363 csci4203/ece4363 22 Task and Function Task Capable of call any function and task Runs with zero or non­zero simulation time Event, delay, and timing control statements are permitted Function Unable to call any task but can call other functions Zero simulation time Not allowed those statements Zero or more arguments which are At least one input should be type of input, output, or inout passed in invocation statements Unable to return a value but can pass multiple values via output or inout statements Only return a single value and can not use either output or inout statements 23 csci4203/ece4363 csci4203/ece4363 Execute Task • • • • Where the real work of the processor is performed case statement is the same as “switch” statement in C sext16: sign exteneded 16­bit value setcc: set the condition code bits for the instructions task execute; begin case (`OPCODE) `ADD: begin if (`IMM_OP == 0) op2 = R[`rs2]; else op2 = sext16(`immed16); op1 = R[`rs1]; result = op1 + op2; R[`rdst] = result[WIDTH­1:0]; setcc(op1, op2, result, 0); end . . . . . . endcase end endtask 24 csci4203/ece4363 csci4203/ece4363 6. Utility operations and functions • sext16, sext17, sext22, sext23: get a sign extended value • setcc: set condition codes • checkcc: check condition codes • print_trace: print traces of execution of the program and monitor the contents of important registers. csci4203/ece4363 csci4203/ece4363 25 Questions?? csci4203/ece4363 csci4203/ece4363 26 Q1: Choose all correct statements for behavioral model 1. Details of precise implementation are hidden 2. Lower level implementation 3. Design in gate or block level 4. Hierarchical interconnection of sub modules csci4203/ece4363 csci4203/ece4363 27 Q1: Choose all correct statements for behavioral model 1. Details of precise implementation are hidden 2. Lower level implementation 3. Design in gate or block level 4. Hierarchical interconnection of sub modules csci4203/ece4363 csci4203/ece4363 28 Q2: Choose all correct statements for function 1. Can call another task 2. Carry out its required duty in zero simulation time 3. Within a function, no event, delay or timing control statements are permitted 4. In the invocation of a function, at least one argument must be passed 5. Can return several values 6. Can not use either output or inout statements csci4203/ece4363 csci4203/ece4363 29 Q2: Choose all correct statements for function in Verilog 1. Can call another task 2. Carry out its required duty in zero simulation time 3. Within a function, no event, delay or timing control statements are permitted 4. In the invocation of a function, at least one argument must be passed 5. Can return several values 6. Can not use either output or inout statements csci4203/ece4363 csci4203/ece4363 30 ...
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This note was uploaded on 01/26/2011 for the course CSCI 4203 taught by Professor Weichunghsu during the Fall '05 term at Minnesota.

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