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Unformatted text preview: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 55, NO. 4, APRIL 2008 369 A Flexible UMTS-WiMax Turbo Decoder Architecture Maurizio Martina , Member, IEEE , Mario Nicola , Member, IEEE , and Guido Masera , Senior Member, IEEE Abstract This work proposes a VLSI decoding architecture for concatenated convolutional codes. The novelty of this architecture is twofold: 1) the possibility to switch on-the-fly from the Universal Mobile Telecommunication System turbo decoder to the WiMax duo-binary turbo decoder with a limited resources overhead com- pared to a single-mode WiMax architecture; and2) the design of a parallel, collision free WiMax decoder architecture. Compared to two single-mode solutions, the proposed architecture achieves a complexity reduction of 17.1% and 27.3% in terms of logic and memory, respectively. The proposed, flexible architecture has been characterized in terms of performance and complexity on a 0.13- m standard cell technology, and sustains a maximum throughput of more than 70 Mb/s. Index Terms Turbo decoder, Universal Mobile Telecommuni- cation System (UMTS), VLSI, WiMax. I. INTRODUCTION I N THE LAST few years, several standards have been proposed for reliable transmission of data over wireless channels (e.g., , ). Besides this, in order to cope with severe transmission environments, typical of wireless systems, channel codes ought to be adopted. Turbo codes  are among the most performing channel codes, and are still a major topic of interest in the scientific literature. Recent works dealing with turbo decoder implementation mainly focus on three aspects. 1) The design of VLSI architectures for duo-binary turbo codes . 2) The design of flexible architectures able to support multiple codes . 3) The design of parallel decoders to sustain very high throughput (tens or hundreds of megabits per second), where the interleaver parallelization is particularly challenging, due to the problem of collisions in memory access . Though current scaled CMOS technologies allow to reach clock frequencies of several hundreds of megahertz, parallelization is still an effective methodology to achieve high throughputs and to approach the long term objective of 1 Gb/s in wireless communications. Furthermore, in high-throughput application-specific integrated circuit (ASIC) design, the adoption of lower frequency parallel architectures instead of higher frequency serial ones is an effective method to combat unreliability and reduce nonrecurrent costs. This work presents a high-performance turbo decoder archi- tecture, which faces parallelization, flexibility, and duo-binary implementation issues while keeping the complexity as re- duced as possible, and achieves a throughput of several tens Manuscript received August 1, 2007; revised November 13, 2007. This work was supported in part by the MEsh ADaptive hOme Wireless nets (MEADOW) project, funded by the Italian government. This paper was recommended byproject, funded by the Italian government....
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