fe_sol_2010

Fe_sol_2010 - Name Solution Computer Architecture EE 4720 Final Examination 11 May 2010 12:30–14:30 CDT Alias A(H1N1 ·· chooo Problem 1(15 pts

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Unformatted text preview: Name Solution Computer Architecture EE 4720 Final Examination 11 May 2010, 12:30–14:30 CDT Alias A(H1N1) ··· chooo! Problem 1 (15 pts) Problem 2 (20 pts) Problem 3 (10 pts) Problem 4 (15 pts) Problem 5 (15 pts) Problem 6 (10 pts) Problem 7 (15 pts) Exam Total (100 pts) Good Luck! Problem 1: (15 pts) The statically scheduled MIPS implementation including the floating-point pipeline is illustrated below. format
 immed
 IR
 Addr
 25:21
 20:16
 IF
 EX
 WB
 MEM
 rsv
 rtv
 IMM
 NPC
 ALU
 Addr
 Data
 Data
 Addr
 D In
 +1
 PC
 Mem
 Port
 Addr
 Data
 Out
 Addr
 Data
 In
 Mem
 Port
 Data
 Out
 rtv
 ALU
 MD
 dst
 dst
 dst
 Decode
 dest. reg
 NPC
 Int Reg File
 FP Reg File
 fd
 fd
 WF
 Addr
 Data
 D In
 WE
 Addr
 Addr
 Data
 fsv
 ftv
 15:11
 20:16
 M6
 we
 we
 Decode
 dest. reg
 ID
 A4
 fd
 we
 fd
 we
 A3
 A2
 A1
 M3
 M4
 M5
 xw
 fd
 we
 xw
 fd
 we
 xw
 M2
 M
 1
 xw
 xw
 fd
 we
 uses FP mul
 uses FP add
 FP load
 Stall
 ID
 "0"
 "2"
 "1"
 30
 2
 "0"
 + 15:0
 29:0
 0
 1
 2
 MTC1
 ( a ) Consider the instruction mtc1 f2, r4 . On the diagram above show the path taken by the data on its trip from r4 to f2 . checked Show path taken by value using a squiggly line on the diagram above. The path is highlighted in red with dashes instead of squiggles. Note that mtc1 uses the rt field for the integer register. The ALU will set its output to the value at its lower input. ( b ) The control logic for the FP pipeline needs only a small change to handle mtc1 . Make that change above. (This has nothing to do with the bypass problem below.) checked Control logic for mtc1 in diagram above. (Ignore bypasses.) Change appears in green . Both the lwc1 and mtc1 instructions take a value from the integer pipeline and write it to the FP register file in the integer WB stage. So for detecting WF structural hazards the same logic can be used with the addition of a box for detecting the mtc1 opcode. 2 ( c ) Add the hardware needed to implement swc1 . Add only datapath, not control logic. checked Datapath for swc1 . The added hardware will provide a way for a value read from the FP register file to hop over to the “Data In” connection on the ME-stage memory port. The EX stage is the critical-path friendly place to do that, the change appears in blue . 3 Problem 1, continued: # Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 lui r1, 0x4593 IF ID EX ME WB ori r1, r1, 0x819c IF ID EX ME WB mtc1 f1, r1 IF ID EX ME WF add.s f2, f2, f1 IF ID A1 A2 A3 A4 WF mtc1 f4, r4 IF ID EX ME WF sub.s f6, f4, f1 IF ID A1 A2 A3 A4 WF swc1 f6, 0(r5) IF ID -------> EX ME WF # Cycle 1 2 3 4 5 6...
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This note was uploaded on 01/25/2011 for the course EE 4720 taught by Professor Staff during the Spring '08 term at LSU.

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Fe_sol_2010 - Name Solution Computer Architecture EE 4720 Final Examination 11 May 2010 12:30–14:30 CDT Alias A(H1N1 ·· chooo Problem 1(15 pts

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