fe_sol_f2008

fe_sol_f2008 - Name Solution Computer Architecture EE 4720...

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Unformatted text preview: Name Solution Computer Architecture EE 4720 Final Examination 9 December 2008, 17:30–19:30 CST Alias ISA were, was I? Problem 1 (10 pts) Problem 2 (15 pts) Problem 3 (20 pts) Problem 4 (15 pts) Problem 5 (20 pts) Problem 6 (20 pts) Exam Total (100 pts) Good Luck! Problem 1: (10 pts) Consider a new floating point instruction nin.d which uses a 5-stage computation unit, N1 - N5 (in contrast to FP add’s A1-A4). The format and register usage for nin.d is the same as the other FP arithmetic instructions. Modify the implementation below so that it can execute nin.d . Hint: This is an easy question, nin.d is just like the FP add and multiply, except it’s 5 stages. checked Add the datapath components, including the functional unit stages (N1 to N5). Solution appears below in blue . checked Add control logic for proper write-float and structural hazard detection (as is already present for add and multiply). Be sure not to break existing instructions. Solution appears below in green . checked The changes must fit in efficiently with what is already present. format immed IR Addr 25:21 20:16 IF EX WB MEM rsv rtv IMM NPC ALU Addr Data Data Addr D In +1 PC Mem Port Addr Data Out Addr Data In Mem Port Data Out rtv ALU MD dst dst dst Decode dest. reg NPC Int Reg File FP Reg File fd fd WF Addr Data D In WE Addr Addr Data fsv ftv 15:11 20:16 M6 we we Decode dest. reg ID A4 fd we fd we A3 A2 A1 M3 M4 M5 xw fd we xw fd we xw M2 M 1 xw xw fd we uses FP mul uses FP add FP load Stall ID "0" "1" 30 2 "0" + 15:0 29:0 1 2 N1 N2 N3 N4 N5 3 "2" "3" uses N xw Datapath Changes Control Logic Changes 2 Problem 2: (15 pts) With the MIPS implementation illustrated below floating-point add and multiply instructions do not raise precise exceptions. If a programmer needs a precise exception for a particular FP instruction he or she can follow it with a test (test for exception) instruction. In the code below test is used to provide a precise exception for mul.d . mul.d f2, f2, f6 test sub.d f16, f14, f20 The test instruction will stall in ID for the minimum number of cycles necessary to ensure a precise exception and will suppress a WF if necessary. ( a ) Add hardware to implement the test instruction. The output of is test is 1 if a test instruction is in ID . Assume there are A4 and M6 outputs that indicate whether an exception was raised. These can be checked in the middle of the cycle. checked Add control logic to stall the pipeline using a new input to the Stall ID or gate. Hint: Very little logic is needed. Changes shown in blue on the next page. When a test instruction is in ID it will stall the pipeline until there is no FP instruction more than three cycles from WF . That is achieved by simply ORing the we bits from stages that are more than three cycles from WF . If an instruction three or less cycles from WF raises an exception there will be enough time to squash any instruction after the test. (See part b.) checked Add logic to suppress WF when necessary....
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This note was uploaded on 01/25/2011 for the course EE 4720 taught by Professor Staff during the Spring '08 term at LSU.

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fe_sol_f2008 - Name Solution Computer Architecture EE 4720...

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