3.1 - COMBINATIONALCIRCUIT SYNTHESIS...

Info iconThis preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon
Copyright © 2004 by M   1 COMBINATIONAL CIRCUIT  SYNTHESIS CLASSIC TWO-LEVEL CIRCUIT SYNTHESIS MULTILEVEL-CIRCUIT SYNTHESIS FACTORIZATION DECOMPOSITION CIRCUIT SYNTHESIS USING BUILDING BLOCKS SHARING BUILDING BLOCKS AMONG OUTPUT  FUNCTIONS MULTIPLEXERS DECODERS LOOK-UP-TABLE LOGIC BLOCKS GENERAL SYNTHESIS METHOD 
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Copyright © 2004 by M   2 CLASSIC TWO-LEVEL CIRCUIT  SYNTHESIS PROCEDURE: THE WORD DESCRIPTION OF DESIRED  BEHAVIOR IS GIVEN. THIS BEHAVIOR IS CONVERTED INTO   SWITCHING (BOOLEAN) FUNTIONS WHICH  LOGICLY RELATE INPUTS TO OUTPUTS. THESE FUNCTIONS ARE MINIMIZED TO  OBTAIN A TWO-LEVEL CIRCUIT REALIZATION,  USING STANDARD GATES FROM A  COMPLETE SET, I.E. EITHER {AND,OR,NOT},  {NAND} OR {NOR} SETS.
Background image of page 2
Copyright © 2004 by M   3 CLASSIC TWO-LEVEL CIRCUIT SYNTHESIS EXAMPLE: DESIGN A FULL-ADDER CIRCUIT. A full-adder is a device that adds in binary, three inputs, A, B, C in and produces, two outputs: the sum, S, of the three inputs and the  carry out, C out . C out  = 1, when at least two inputs equal to 1. The output functions are:   S = A   B   C in  , C out = A B + A C in  + B C in + A B C in Minimizing these  functions, using k-maps or any other method,we  obtain S = A   B   C in  , C out = A B + A C in  + B C in Using {AND,OR,NOT} gates, the minimal two level circuits are  shown on next slide.
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Copyright © 2004 by M   4 CLASSIC TWO-LEVEL CIRCUIT SYNTHESIS EXAMPLE: DESIGN A FULL-ADDER CIRCUIT. (Continues)
Background image of page 4
Copyright © 2004 by M   5 CLASSIC TWO-LEVEL CIRCUIT SYNTHESIS EXAMPLE: DESIGN A FULL-ADDER CIRCUIT. (Continues) Using {NAND} complete set, we obtain the circuit Remark : A two-level AND-OR circuit is transformed into a two- level NAND-NAND circuit by replacing AND, OR gates with  NAND’s
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Copyright © 2004 by M   6  MULTILEVEL-CIRCUIT SYNTHESIS FACTORIZATION By finding common factors in the terms of the sum-of-products  expression, it is possible to use gates with less fan-in. However,  the resulting circuit has more propagation delay than the two- level-logic equivalent.  For example: Consider the SUM function. If only two-input gates  are available, then SUM = A   B   C in  = (A !B + !A B) !C in  + (!A ! B + A B) C in   = (A   B)   C in  which produces the circuit C in SUM A B
Background image of page 6
Copyright © 2004 by M   7 MULTILEVEL-CIRCUIT SYNTHESIS FACTORIZATION (continues) Another example: The parity check circuit of 4 variables F(A,B,C,D) = A   B   C   D
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 8
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 01/27/2011 for the course ECSE 323 taught by Professor Rk during the Spring '10 term at McGill.

Page1 / 22

3.1 - COMBINATIONALCIRCUIT SYNTHESIS...

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online