4.2 - 1 ECSE-323 Digital System Design VHDL Lecture#2...

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1 McGill University ECSE-323 Digital System Design / Prof. J. Clark ECSE-323 Digital System Design VHDL Lecture #2
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2 McGill University ECSE-323 Digital System Design / Prof. J. Clark Simple Concurrent Assignment Statements signal <= expression; Examples: A_Out <= not ( A_In or B_in ) and Enable; Data <= X nor D2 xor (flag_A and flag_B); •The “not” operator has the highest precedence. •Operators in parentheses are evaluated first. •All binary operators have equal precedence. •Operators with the same precedence are evaluated left-to-right.
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3 McGill University ECSE-323 Digital System Design / Prof. J. Clark Other Types of Assignment Statements The descriptions of complex circuits can be tedious to write using just simple assignment statements So, VHDL gives additional types of signal assignment statements. These other types of statements can also better direct synthesis programs in generating hardware
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4 McGill University ECSE-323 Digital System Design / Prof. J. Clark Forms of signal assignment statements: Simple Concurrent Assignment Selected Assignment Conditional Assignment Component Instantiation Generate Statements Process Blocks
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5 McGill University ECSE-323 Digital System Design / Prof. J. Clark Selected Signal Assignment Statements A selected signal assignment is a means of conveniently describing multiplexer structures with Dsel select Y <= A when "00”, B when "01”, C when "10”, D when others ; Order is not Important!
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6 McGill University ECSE-323 Digital System Design / Prof. J. Clark Note: All conditions must be defined in a selected signal assignment, otherwise your code will not conform to the VHDL standard and you will probably get an error from whatever software happens to be reading your code. Coverage of all conditions can be tricky to ensure – which is why the “ when others ” clause is useful
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7 McGill University ECSE-323 Digital System Design / Prof. J. Clark An example of possible problems - with Dsel select Y <= A when “00”, B when “01”, C when “10”, D when “11”; This assignment statement will give an error if Dsel is of type STD_LOGIC_VECTOR (but not if Dsel is of type BIT_VECTOR ). Why? Because the type of signal Dsel has more possible values than just 0 and 1 (e.g. a high-impedance value – Z) so that not all possibilities are covered.
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