9.1 - 1 ECSE-323 Digital System Design VHDL Lecture #3...

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1 McGill University ECSE-323 Digital System Design / Prof. J. Clark ECSE-323 Digital System Design VHDL Lecture #3
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2 McGill University ECSE-323 Digital System Design / Prof. J. Clark VHDL Modeling Styles Behavioral – used for functional design without regard to implementation Structural – used to describe hardware structures Mixed structural/behavioral
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3 McGill University ECSE-323 Digital System Design / Prof. J. Clark Behavioral Style of VHDL Descriptions Describes circuit function in abstract way without regard to actual form of implementation Usually described using process block statements which encapsulate collections of actions executed in sequence Similar to standard programming languages like C
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4 McGill University ECSE-323 Digital System Design / Prof. J. Clark Process block – Syntax process_label : process (sensitivity list) -- declarations begin -- sequential statements end process ;
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5 McGill University ECSE-323 Digital System Design / Prof. J. Clark The first line of the process statement includes a label , the keyword process , and an optional list of signals , known as the sensitivity list . process_label : process (sensitivity list)
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6 McGill University ECSE-323 Digital System Design / Prof. J. Clark A process with a sensitivity list is evaluated during simulation whenever an event occurs on any of the signals in the sensitivity list ( and only then ). If a process has no sensitivity list then it is evaluated when an event occurs on any signal.
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7 McGill University ECSE-323 Digital System Design / Prof. J. Clark Sensitivity lists are only used for speeding up simulations . They are ignored by synthesis programs. Why? Hardware synthesis needs to know about all signals, not just the active ones. Simulation, on the other hand, only needs to know about active signals.
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8 McGill University ECSE-323 Digital System Design / Prof. J. Clark In a typical circuit application, a process will include in its sensitivity list all inputs that have asynchronous behavior . These asynchronous inputs may include clock signal(s) reset signals inputs to blocks of combinational logic
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