9.2 - 1 ECSE-323 Digital System Design VHDL Lecture#4...

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1 McGill University ECSE-323 Digital System Design / Prof. J. Clark ECSE-323 Digital System Design VHDL Lecture #4
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2 McGill University ECSE-323 Digital System Design / Prof. J. Clark Example: 4-bit Counter with Control Signals signal count : integer range 0 to 15; begin –- begin architecture block counter1 : process (reset,Clk) begin if reset = ‘1' then count <= 0; elsif Clk = '1' and Clk'event then if enable = ‘1’ then if load = ‘1’ then count <= ldata; elsif updown = ‘1’ then count <= count + 1; else count <= count 1; end if; -- if load end if; -- if enable end if; -- if reset end process ; load ldata count up/down Clk enable reset
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3 McGill University ECSE-323 Digital System Design / Prof. J. Clark How to Enable a Clocked Operation: This is the right way to enable a clocked operation elsif Clk = '1' and Clk'event then if enable = ‘1’ then -- do stuff when enabled elsif Clk = '1' and enable = ‘1’ and Clk'event then -- do stuff when enabled This is a bad way to enable a clocked operation Why is this type of VHDL construct bad? It may confuse the compiler. It may create a gated clock (causing clock skew and glitches and slowing down the system)
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4 McGill University ECSE-323 Digital System Design / Prof. J. Clark architecture BEHAVIORAL of gate_clock is signal GATECLK: STD_LOGIC; begin GATECLK <= (IN1 and IN2 and CLK); GATE_PR: process (GATECLK,DATA,LOAD) begin if (GATECLK'event and GATECLK = '1') then if (LOAD = '1') then OUT1 <= DATA; end if; end if; end process; end BEHAVIORAL; example is from the Xilinx Synthesis and Simulation Design Guide - http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/sim.html Implementation of a Gated Clock the signal GATECLK will be delayed relative to CLK
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5 McGill University ECSE-323 Digital System Design / Prof. J. Clark architecture BEHAVIORAL of gate_clock is signal ENABLE: STD_LOGIC; begin ENABLE <= IN1 and IN2 and LOAD; EN_PR: process (ENABLE,DATA,CLOCK) begin if (CLOCK'event and CLOCK = '1') then if (ENABLE = '1') then DOUT <= DATA; end if; end if; end process; end BEHAVIORAL; Implementation of an Enabled Clock example is from the Xilinx Synthesis and Simulation Design Guide - http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/sim.html
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6 McGill University ECSE-323 Digital System Design / Prof. J. Clark Arithmetic Signal Types and Operations std_logic_vector(N downto 0) defines an (N+1)-bit unsigned binary number whose LSB is bit 0 and MSB is bit N. S<=X+Y; This expression describes an (N+1)-bit adder without carry in or carry out. The signal S has N+1 bits (and not N+2 ).
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McGill University ECSE-323 Digital System Design / Prof. J. Clark Note: VHDL requires that at least one of the operands on the RHS have the same bit length as the LHS. To add in a Carry input and output we can write:
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This note was uploaded on 01/27/2011 for the course ECSE 323 taught by Professor Rk during the Spring '10 term at McGill.

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9.2 - 1 ECSE-323 Digital System Design VHDL Lecture#4...

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