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# 10.2 - 1 ECSE-323 Digital System Design Datapath/Controller...

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1 McGill University ECSE-323 Digital System Design / Prof. J. Clark ECSE-323 Digital System Design Datapath/Controller Lecture #2

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2 McGill University ECSE-323 Digital System Design / Prof. J. Clark Datapath/Controller architecture Control inputs Control signals Control outputs Status signals Data inputs Data outputs Control Unit Datapath Clock
3 McGill University ECSE-323 Digital System Design / Prof. J. Clark General Approach to Design of Datapath/Controller Systems 1. Describe the function to be performed 2. Determine what datapath elements are needed 3. Specify the interconnections of the datapath elements 4. Identify the controller input and output signals 5. Sketch the sequence of control signal values needed to carry out the desired function 6. Design a Finite State Machine that will implement the required sequence 7. Simulate (by hand or by computer) the complete system to verify the proper execution of the desired function. Go back to step if there are any problems. 8. Implement and test complete system. Go back to step 2 if there are any problems with the implementation

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4 McGill University ECSE-323 Digital System Design / Prof. J. Clark Case Study #1 - Digital Filter We wish to design recursive digital filter that implements the equation: y(n)=a * y(n-1) + b * x(n) + c * x(n-1) where the coefficients a,b,c are stored in registers. You can have as many registers and multiplexers as you want, but assume that you only have available one multiplier and one adder block. Assume that an external input named Sample goes high whenever a new sample value on x is available.
5 McGill University ECSE-323 Digital System Design / Prof. J. Clark 1. y = y (from previous cycle) 2. y = 0 + a*y 3. y = y + b*x(n) 4. y = y + c*x(n-1) STEP 1: Describe the function to be performed y(n)=a*y(n-1) + b * x(n) + c*x(n-1)

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6 McGill University ECSE-323 Digital System Design / Prof. J. Clark Registers to store x(n),x(n-1),y(n), a,b,c Adder Multiplier (or combination Multiply-Accumulator) Multiplexers STEP 2: Determine the Datapath elements needed
7 McGill University ECSE-323 Digital System Design / Prof. J. Clark STEP 3: Specify the interconnections of the datapath AReg BReg CReg XReg Multiplier Adder MUX MUX YReg MSel1 MSel2 LD_Y CLR_Y XOldReg LD_X CLR_X MUX MSel3 0 Y Y(n) X(n) X(n-1)

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8 McGill University ECSE-323 Digital System Design / Prof. J. Clark STEP 4: Identify the controller inputs and outputs CONTROLLER Sample reset clock MSel1 MSel2 MSel3 LD_X CLR_X LD_Y CLR_Y DONE
9 McGill University ECSE-323 Digital System Design / Prof. J. Clark STEP 5: Sketch the sequence of control signal values 1. Wait for Sample to go low. 2. Wait for Sample to go high. 3. Set Msel1 to the a input, Msel2 to the Y input, and MSel3 to the 0 input (thus, the output of the adder will be a*y(n-1)) . 4. Assert LD_Y to store the result of the multiply-accumulate into the output (Y) register.

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• Spring '10
• Rk
• Central processing unit, McGill University, McGill University ECSE-323, Prof. J. Clark, University ECSE-323 Digital

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10.2 - 1 ECSE-323 Digital System Design Datapath/Controller...

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