13.2 - 1 ECSE-323 Digital System Design Sequential Testing...

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1 McGill University ECSE-323 Digital System Design / Prof. J. Clark ECSE-323 Digital System Design Sequential Testing Lecture #2
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2 McGill University ECSE-323 Digital System Design / Prof. J. Clark Even with scan-path methods, the testing of modern chips and systems is very costly and time-consuming. One approach to reducing the cost and complexity of external testers is to put circuitry on-chip to do a lot of the testing. This approach is known as Built-In Self-Test (BIST)
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3 McGill University ECSE-323 Digital System Design / Prof. J. Clark Increasing chip logic-to-pin ratio – harder observability Increasingly dense devices and faster clocks Increasing test generation and application times Increasing size of test vectors stored in ATE Expensive ATE needed for 1 GHz clocking chips Hard testability insertion – designers are unfamiliar with gate-level logic, since they design at behavioral level In-circuit testing no longer technically feasible Shortage of test engineers Circuit testing cannot be easily partitioned Testing difficulties addressed by BIST
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4 McGill University ECSE-323 Digital System Design / Prof. J. Clark 11.1. BUILT-IN SELF-TEST (BIST) Self-test is initiated by driving the INIT pin high when RESET transitions from high to low. No bus cycles are run by the Pentium processor during self-test. The duration of self-test is approximately 2^19 core clocks. [2.6 msec with 200MHz clock] Approximately 70% of the devices in the Pentium processor are tested by BIST. Upon completion of BIST, the cumulative result of all tests are stored in the EAX register. If EAX contains 0h, then all checks passed; any non-zero result indicates a faulty unit. Note that if an internal parity error is detected during BIST, the processor will assert the IERR# pin and attempt to shutdown. From the Pentium Developers Manual (ca 1997) BIST is used widely in modern chips
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5 McGill University ECSE-323 Digital System Design / Prof. J. Clark What can be put on-chip? Test vector generation • FDTS test vector tables • random test vector generation Test vector presentation • scan-path control Test response analysis • FDTS response tables • Response signature analysis
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6 McGill University ECSE-323 Digital System Design / Prof. J. Clark For circuits with large numbers of inputs and outputs, storage of the FDTS and test responses on-chip is impractical . Thus, the generation of random test vectors is preferred.
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McGill University ECSE-323 Digital System Design / Prof. J. Clark The idea behind using random vectors is that a given vector of them will probably cover some of the faults.
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13.2 - 1 ECSE-323 Digital System Design Sequential Testing...

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