ICS233_Lecture4 Slides

ICS233_Lecture4 Slides - Computer Architecture &...

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1 Lecture Slides on Computer Architecture ICS 233 @ Dr A R Naseer 1 MIPS MIPS PROCESSOR PROCESSOR INSTRUCTION SET INSTRUCTION SET ICS 233 ICS 233 Computer Architecture & Computer Architecture & Assembly Language Assembly Language Lecture Slides on Computer Architecture ICS 233 @ Dr A R Naseer 2 ICS 233 ICS 233 Computer Architecture & Computer Architecture & Assembly Language Assembly Language Lecture 4 Lecture 4
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2 Lecture Slides on Computer Architecture ICS 233 @ Dr A R Naseer 3 Lecture Outline ± MIPS Processor Overview ± MIPS Instruction Formats ± MIPS Addressing Modes Lecture Slides on Computer Architecture ICS 233 @ Dr A R Naseer 4 The MIPS CPU ¾ MIPS CPU originated from research project at Stanford, most successful and flexible CPU design of the 1990s ¾ MIPS CPUs were found in SGI graphics workstations, Windows CE handhelds, CISCO routers, and Nintendo 64 video game consoles ¾ MIPS CPUs follow the RISC (Reduced Instruction Set Computer) design principle: limited repertoire of machine instructions limited arithmetical complexity supported extensive supply of CPU registers (reduce memory accesses)
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3 Lecture Slides on Computer Architecture ICS 233 @ Dr A R Naseer 5 MIPS Processor Architecture ¾ MIPS processor consists of an integer processing unit (CPU) and a collection of coprocessors that perform ancillary tasks or operate on other types of data such as floating-point numbers. ¾ Coprocessor 0 handles exceptions, interrupts, and the virtual memory system ¾ Coprocessor 1 is the floating-point unit. ¾ MIPS is a load-store architecture , which means that only load and store instructions access memory. ¾ Computation instructions (like arithmetic & logical) operate only on values in registers. Lecture Slides on Computer Architecture ICS 233 @ Dr A R Naseer 6 Overview of the MIPS Processor Memory Up to 2 32 bytes = 2 30 words 4 bytes per word $0 $1 $2 $31 Hi Lo ALU F0 F1 F2 F31 FP Arith EPC Cause BadVaddr Status EIU FPU TMU Execution & Integer Unit ( CPU ) Floating Point Unit ( Coproc 1 ) Trap & Memory Unit ( Coproc 0 ) . . . . . . Integer mul/div Arithmetic & Logic Unit 32 General Purpose Registers Integer Multiplier/Divider 32 Floating- Point Registers Floating-Point Arithmetic Unit
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4 Lecture Slides on Computer Architecture ICS 233 @ Dr A R Naseer 7 MIPS CPU Registers ¾
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ICS233_Lecture4 Slides - Computer Architecture &...

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