ICS233_Lecture6 Slides

# ICS233_Lecture6 Slides - Computer Architecture Assembly...

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1 Lecture Slides on Computer Architecture ICS 233 @ Dr A R Naseer 1 MIPS MIPS PROCESSOR PROCESSOR INSTRUCTION SET INSTRUCTION SET ICS 233 ICS 233 Computer Architecture & Computer Architecture & Assembly Language Assembly Language Lecture Slides on Computer Architecture ICS 233 @ Dr A R Naseer 2 ICS 233 ICS 233 Computer Architecture & Computer Architecture & Assembly Language Assembly Language Lecture 6 Lecture 6

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2 Lecture Slides on Computer Architecture ICS 233 @ Dr A R Naseer 3 Lecture Outline ± MIPS Shift Instructions ± MIPS Multiply & Divide Instructions ± MIPS Data Transfer Instructions Lecture Slides on Computer Architecture ICS 233 @ Dr A R Naseer 4 Shift Operations Shifting is to move all the bits in a register left or right Shifts by a constant amount: sll, srl, sra sll/srl mean shift left/right logical by a constant amount The 5-bit shift amount field is used by these instructions sra means shift right arithmetic by a constant amount The sign-bit (rather than 0) is shifted from the left shift-in 0 . . . shift-out MSB sll 32-bit register . . . shift-in 0 shift-out LSB srl . . . shift-in sign-bit shift-out LSB sra
3 Lecture Slides on Computer Architecture ICS 233 @ Dr A R Naseer 5 \$s1 = 0x0000abcd \$s1 = 0xcd123400 Shift Instructions f = 7 sa = 0 rd = \$s1 rt = \$s2 rs = \$s3 op = 0 \$s1 = \$s2 >> \$s3 srav \$s1,\$s2,\$s3 f = 6 sa = 0 rd = \$s1 rt = \$s2 rs = \$s3 op = 0 \$s1 = \$s2>>>\$s3 srlv \$s1,\$s2,\$s3 f = 4 f = 3 f = 2 f = 0 sa = 0 sa = 10 sa = 10 sa = 10 rd = \$s1 rd = \$s1 rd = \$s1 rd = \$s1 rt = \$s2 rt = \$s2 rt = \$s2 rt = \$s2 rs = \$s3 rs = 0 rs = 0 rs = 0 op = 0 \$s1 = \$s2 << \$s3 sllv \$s1,\$s2,\$s3 op = 0 \$s1 = \$s2 >> 10 sra \$s1, \$s2, 10 op = 0 \$s1 = \$s2>>>10 srl \$s1,\$s2,10 op = 0 \$s1 = \$s2 << 10 sll \$s1,\$s2,10 R-Type Format Meaning Instruction Shifts by a variable

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ICS233_Lecture6 Slides - Computer Architecture Assembly...

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