ch6_2 - COMBINATIONAL LOGIC DESIGN PRACTICE(Chapter 6...

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3-22-2010 COCO Ch. 6, Part 2 1 COMBINATIONAL LOGIC DESIGN & PRACTICE (Chapter 6, continued)
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3-22-2010 COCO Ch. 6, Part 2 2 What to we need to know about an SSI circuit? Block Diagram: function Truth-table: input-output Logic gate diagram : how it does it Circuit diagram : how to build it Dynamic behavior (timing diagram): Applications: where to use it Common SSI circuits: programmable logic devices (PLDs) encoder, decoder , bus , exor, comparator, mux, demux, adder, subtractor, Arithmetic and Logic Unit (ALU)
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3-22-2010 COCO Ch. 6, Part 2 3 PLDs ( 6.3 ) Combinational Programmable Logic Devices
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3-22-2010 COCO Ch. 6, Part 2 4 Implementing Larger Circuits: Programmable Logic Arrays Discrete modules on a circuit board: messy connections error prone space and power and intensive Programmable Logic Device: Buy a single programmable logic array (PLA) chip Customize this chip to implement our function E.g., download espresso output to a “ PLA programmer .”
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3-22-2010 COCO Ch. 6, Part 2 5 Programmable Logic Arrays ( PLA s) • Any combinational logic function can be realized as a sum of products. • Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections.
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3-22-2010 COCO Ch. 6, Part 2 6 Compact representation of a PLA
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3-22-2010 COCO Ch. 6, Part 2 7 O1 = I1•I2 + I1’•I2’•I3’•I4’ O2 = I1•I3’+ I1’•I3•I4 + I2 O3 = I1•I2 + I1•I3’ + I1’•I2’•I4’ NB AND lines vertical OR lines horizontal
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3-22-2010 COCO Ch. 6, Part 2 8 4 x 3 PLA (programable logic array) with six product terms. Note 4x2x6 + 6x3 fuses (nonvolatile memory cells). Implements sums of products. Suppose, instead, that the: Number of input signals Ni = 16 Number of AND gates Na = 56 Number of OR gates No = 8 How many fuses ?
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3-22-2010 COCO Ch. 6, Part 2 9 Number of fuses Number of input signals Ni = 16 Number of AND gates Na = 56 Number of OR gates No = 8 AND-plane OR-plane Number of fuses = 2 x Ni x Na + Na x No = 2 x16 x 56 + 56 x 8 = 2240
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3-22-2010 COCO Ch. 6, Part 2 10 Other PLDs: PAL, GAL, CMOS-PLD and EEPLD PLA s are AND-OR arrays with permanent fuses. Their size is limited by the necessary connections. In PAL , fused connections are also set permanently, but it has a fixed OR array and bidirectional I/O pins . In GAL , fuses are non-volatile memory cells. CMOS PLDs have wired logic instead of AND gates. EEPLD are electrically programmed using a capacitor. Beware: “PLA” is sometimes used as a generic term for all of these.
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3-22-2010 COCO Ch. 6, Part 2 11 Logic symbol for PAL16L8 Pins: 10 I 2 O 6 I /O 2 ? 20 ?
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3-22-2010 COCO Ch. 6, Part 2 12 Programmable Array Device ( PAL* ) Up to 16 inputs and 8 outputs, with only 20 pins! 7 AND gates permanently connected to each OR gate. Word (AND) lines are vertical, OR lines horizontal 8x8x8x4=2 11 = 2048 fuses
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3-22-2010 COCO Ch. 6, Part 2 13 Pin 15 is a bidirectional Pin (IO5). When Output_Enable is Low it is Input; when High, it is Output I/O PINS (Control to determine if I/O pin is I or O is via an Input pin)
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3-22-2010 COCO Ch. 6, Part 2 14 Three-state PAL outputs are inverted • The three state I/O buffer is an inverting buffer (note the bubble) • I/O pins can be used as Input, Output, or Three-state output (to a bus) • Output pins can be used as Output or as Three-state output (to a bus)
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This note was uploaded on 01/27/2011 for the course ECSE 2610 taught by Professor Ji during the Spring '08 term at Rensselaer Polytechnic Institute.

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ch6_2 - COMBINATIONAL LOGIC DESIGN PRACTICE(Chapter 6...

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