ch6_3 - Combinational Design (CH. 6) Last Monday: PLA, PAL,...

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March 25, 2010 COCO Ch 6 Part 3 1 Combinational Design (CH. 6) Last Monday: PLA, PAL, GAL, Bidirectional pins, Output polarity control (XOR), Wired Logic, EEPLD, Decoders, Cascading decoders, Encoders, Buses Today: Chapter 6, Sections 5-9 6.5 Encoders 6.6 Three-state devices and buses 6.7 Multiplexers 6.8 EXOR and Parity Circuits 6.9 Comparators 6.10 Adders, Subtractors and ALUs
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March 25, 2010 COCO Ch 6 Part 3 2 Review: PAL with IO pins used for input IO6 = (IO4•IO5’)’ Here I4 determines which IO pin is input and which is output. I4 is High, so Enable_IO6 is High, and Enable_IO4 & _IO5 are low IN IN OUT H
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March 25, 2010 COCO Ch 6 Part 3 3 Review: 5-to-32 Decoder cascading 74x138 3-to-8 decoders Decode 11011 Leftmost two bits enable one of four decoders. Here N4,N3 = 11 select 24-31 decoder , and N2,N1,N3 = 011 decodes to Y3
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March 25, 2010 COCO Ch 6 Part 3 4 Cascading Priority Encoders 32-input priority encoder. Outputs RA4:RA0, and RGS EO enables lower decoders if there is no higher input GS_L if some input low Logic complicated: work through it with examples! MSB
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March 25, 2010 COCO Ch 6 Part 3 5 Three-state buffers: active-high and active-low enable , inverting and non-inverting output
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March 25, 2010 COCO Ch 6 Part 3 6 74x541 octal buffers for a microprocessor input port: INSEL selects one of two user inputs to read from
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March 25, 2010 COCO Ch 6 Part 3 7 74x 245 Bidirectional: octal 3-state transceiver A Æ B B Æ A G_L 0 0 DIR 1 0 Note hysteresis symbol: ON after OFF V1 A Æ BB Æ A ON ON V2 t Å V1 V2 Æ A B A Æ B B Æ A
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March 25, 2010 COCO Ch 6 Part 3 8 Four two-bit buses! All the buses are driven either by a constant, or by one of the other buses. The source bus is driven with 00.
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March 25, 2010 COCO Ch 6 Part 3 9 PLD transceivers for four 2-bit buses. OE are individual output enable signals. MOE is the master output enable signal. Note special provision for the A bus (not enough I/O pins).
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March 25, 2010 COCO Ch 6 Part 3 10 MULTIPLEXERS 6.7
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March 25, 2010 COCO Ch 6 Part 3 11 What is a mux? • A mux is a digital switch that connects one of n inputs to its single output. • The Inputs can be one or more bits wide. • A Control signal selects the active input. • An Enable signal enables the mux to do its thing. •A demultiplexer does the opposite: it routes a signal to one of several destinations .
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March 25, 2010 COCO Ch 6 Part 3 12 A mux with n sources, each b bits wide.
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March 25, 2010 COCO Ch 6 Part 3 13 2:1, 4:1, 8:1 1-bit MUXes 2:1 MUX I 0 I 1 A Z I 0 A I 1 I 2 I 3 B Z 4:1 MUX I 0 A I 1 I 2 I 3 B Z 8:1 MUX C I 4 I 5 I 6 I 7
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March 25, 2010 COCO Ch 6 Part 3 14 Cascading MUXes 4:1 MUX 4:1 MUX 8:1 MUX 2:1 MUX 0 1 2 3 0 1 2 3 S S 1 S 0 S 1 S 0 Z A C B I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 0 1
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March 25, 2010 COCO Ch 6 Part 3 15 74x151 8-input, 1-bit mux select = 101 inputs output enable
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March 25, 2010 COCO Ch 6 Part 3 16 Truth table for a 74x157 2-input, 4-bit multiplexer
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March 25, 2010 COCO Ch 6 Part 3 17 74x157 2-input, 4-bit multiplexer Note that input pins are interlaced
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March 25, 2010 COCO Ch 6 Part 3 18 Combining a decoder with 4 74x151s for a 32 input, 1-bit mux XA0 – XA2 select a bit XA3 – XA4 enable one of the 151s Input can be one bit of 32 32-bit registers A, B, C are SELECT lines Note EN_LO QUIZ NEXT
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March 25, 2010 COCO Ch 6 Part 3 19 QUIZ Suppose XA = 1A Input X = F0E4 ADB7 XOUT = ?
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ch6_3 - Combinational Design (CH. 6) Last Monday: PLA, PAL,...

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