hw06 - addends (i.e., the bits to be added), and include...

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___________ ____________________________ _ 1/1 Section name Homework # 6 Due Wednesday March 17, 2010 in Studio ECSE-2610 Computer Components and Operations 1). (8) Write a VHDL program to create an AND gate using the LogicWorks VHDL wizard. Call it by your LAST NAME. Label the first input by the first letter of your last name, the second input by the second letter, and the output by the third letter. So if your last name happens to be LAST, the inputs are L and A, and the output is S. If your name has fewer than three letters, be inventive. Let the propagation delay of the gate be 10 ns. Using the I/O panel, cycle your program through 00, 01, 11, 10 a couple of times, and use the LW Select All, copy and paste commands to copy the resulting Timing Panel and your complete VHDL code into your assignment. 2) (8) Write a VHDL program to simulate a one-bit adder. Use the first two letters of your last name to label the
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Unformatted text preview: addends (i.e., the bits to be added), and include your last name in the name of the circuit. A full adder has three inputs: the two bits to be added, and carry_in. It has two outputs: sum and carry_out. Include your VHDL code in your assignment. Toggle the I/O panel buttons until sum=0 and carry_out=1, and use PrtSc to include a copy of the timing display showing all your variables and your VHDL code. 3. (9) Preparation for the next studio. The functions implemented by HA are: S = A B; C=A B. Write down the Boolean expressions for Cout, S1 and S0 (use only AND, OR, and XOR) , then fill the truth table below (let Cin=0 ) A1 A0 B1 B0 Cout S1 S0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 HA HA HA HA HA S1 S0 Cout Cin A B S C A1 B1 A0 B0...
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This note was uploaded on 01/27/2011 for the course ECSE 2610 taught by Professor Ji during the Spring '08 term at Rensselaer Polytechnic Institute.

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