L6-1 - ELEC152 Computer Organization Lecture 6: Enhancing...

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ELEC152 Computer Organization ecture 6: Enhancing Performance Lecture 6: Enhancing Performance with Pipelining rofessor George Yuan Professor George Yuan Office: Rm. 2527 Email:[email protected]
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Performance Enhancement Parallelism Several jobs are executed at the same time Two different ways to do parallelism: Pipelining – parallelism among several instructions Parallel processing or multi-processing – arallelism among several processors usually parallelism among several processors, usually duplicated processors/hardware ELEC152 Computer Organization Spring 2010 Page 2
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Pipelining example Laundry Analogy Ann, Brian, Cathy, Dave each have one load of clothes wash dry and fold A B C D to wash, dry, and fold Washer takes 30 minutes Dryer takes 30 minutes “Folder” takes 30 minutes “Stasher” takes 30 minutes put clothes into drawers ELEC152 Computer Organization Spring 2010 Page 3 to put clothes into drawers
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Sequential Laundry 6 PM 7 8 9 10 11 12 1 2 AM 30 T Time 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 a s k B A O C D r d e Sequential laundry takes 8 hours for 4 loads If they learned pipelining, how long would laundry take? r ELEC152 Computer Organization Spring 2010 Page 4
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Pipelined Laundry: Start work ASAP 12 2 AM 6 PM 7 8 9 10 11 1 T a Time A 30 30 30 30 30 30 30 s k B O C D r d e Pipelined laundry takes 3.5 hours for 4 loads! r ELEC152 Computer Organization Spring 2010 Page 5
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Pipelining Lessons Pipelining doesn’t help latency of single task, it helps throughput of 6 PM 78 9 entire workload Multiple tasks operating imultaneously using different Time 30 30 30 30 30 30 30 T a simultaneously using different resources Potential speedup = Number pipe A s k stages Pipeline rate limited by slowest pipeline stage B C O pp g Unbalanced lengths of pipe stages reduces speedup D r d e Time to “ fill ” pipeline and time to drain ” it reduces speedup Stall for Dependences r ELEC152 Computer Organization Spring 2010 Page 6
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The Five Stages of Load Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Ifetch Reg/Dec Exec Mem Wr Load E.g. Lw $s0, table1($s1) Ifetch: Instruction Fetch Fetch the instruction from the Instruction Memory Reg/Dec: Registers Fetch and Instruction Decode Exec: Calculate the memory address Mem: Read the data from the Data Memory ELEC152 Computer Organization Spring 2010 Page 7 Wr: Write the data back to the register file
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Pipelining to improve performance Improve performance by increasing instruction throughput Instruction class Instruction fetch Reg. read ALU op. Data Access Reg. Write Total time Load word (lw) 200ps 100ps 200ps 200ps 100ps 800ps tore word (lw) 00ps 00ps 00ps 00ps 00ps Store word (lw) 200ps 100ps 200ps 200ps 700ps R-format (add, 200ps 100ps 200ps 100ps 600ps sub, and, or slt) Branch (beq) 200ps 100ps 200ps 500ps Total time for each instruction calculated from the time for each component (assuming the mux, control unit, PC access, and sign extension unit has not delay) ELEC152 Computer Organization Spring 2010 Page 8
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Pipelining 200 400 600 800 1000 1200 1400 1600 1800 Program execution
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This note was uploaded on 01/28/2011 for the course ELEC 152 taught by Professor Chan during the Fall '09 term at HKUST.

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L6-1 - ELEC152 Computer Organization Lecture 6: Enhancing...

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