M68HC11ERG - Reference Guide M68HC11ERG/AD Rev. 1, 6/2002...

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Unformatted text preview: Reference Guide M68HC11ERG/AD Rev. 1, 6/2002 M68HC11E Series Programming Reference Guide Block Diagram MODA/ MODB/ LIR VSTBY XTAL EXTAL E IRQ XIRQ/VPPE* RESET OSC MODE CONTROL CLOCK LOGIC INTERRUPT LOGIC ROM OR EPROM (SEE TABLE) PULSE ACCUMULATOR COP PAI OC2 OC3 OC4 OC5/IC4/OC1 IC1 IC2 PERIODIC INTERRUPT IC3 TIMER SYSTEM M68HC11 CPU EEPROM (SEE TABLE) RAM (SEE TABLE) R/W AS BUS EXPANSION ADDRESS ADDRESS/DATA SERIAL PERIPHERAL INTERFACE SPI SERIAL COMMUNICATION INTERFACE SCI VDD VSS STRB STRA SS SCK MOSI MISO TxD RxD STROBE AND HANDSHAKE PARALLEL I/O VRH VRL A/D CONVERTER CONTROL PORT A PORT B PORT C CONTROL PORT D PORT E STRB/R/W PA7/PAI PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1 PA3/OC5/IC4/OC1 PA2/IC1 PA1/IC2 PA0/IC3 PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TxD PD0/RxD STRA/AS PC7/ADDR7/DATA7 PC6/ADDR6/DATA6 PC5/ADDR5/DATA5 PC4/ADDR4/DATA4 PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 PC1/ADDR1/DATA1 PC0/ADDR0/DATA0 * VPPE applies only to devices with EPROM/OTPROM. DEVICE MC68HC11E0 MC68HC11E1 MC68HC11E9 MC68HC711E9 MC68HC11E20 MC68HC711E20 MC68HC811E2 RAM 512 512 512 512 768 768 256 ROM -- -- 12 K -- 20 K -- -- PE7/AN7 PE6/AN6 PE5/AN5 PE4/AN4 PE3/AN3 PE2/AN2 PE1/AN1 PE0/AN0 EPROM -- -- -- 12 K -- 20 K -- EEPROM -- 512 512 512 512 512 2048 Motorola, Inc., 2002 M68HC11ERG/AD Devices Covered in This Reference Guide Device MC68HC11E0 MC68HC11E1 MC68HC11E9 MC68HC711E9 MC68HC11E20 MC68HC711E20 MC68HC811E2 RAM 512 512 512 512 768 768 256 ROM -- -- 12K -- 20K -- -- EPROM -- -- -- 12K -- 10K -- EEPROM -- 512 512 512 512 512 2048 M68HC11E Series Programming Model 7 15 A 0 D IX IY SP PC 7 B 0 0 8-BIT ACCUMULATORS A & B OR 16-BIT DOUBLE ACCUMULATOR D INDEX REGISTER X INDEX REGISTER Y STACK POINTER PROGRAM COUNTER 7 S 0 X H I N Z V C CONDITION CODES CARRY/BORROW FROM MSB OVERFLOW ZERO NEGATIVE I-INTERRUPT MASK HALF CARRY (FROM BIT 3) X-INTERRUPT MASK STOP DISABLE 2 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD Crystal Dependent Timer Summary Crystal Dependent Timer Summary Selected Crystal CPU Clock Cycle Time (E) (1/E) Common XTAL Frequencies 4.0 MHz 1.0 MHz 1000 ns 8.0 MHz 2.0 MHz 500 ns 12.0 MHz 3.0 MHz 333 ns Pulse Accumulator (in Gated Mode) (E/26) (E/214) 1 count -- overflow -- PR[1:0] (E/1) (E/216) (E/4) (E/218) (E/8) (E/219 ) 00 1 count-- overflow -- 01 1 count-- overflow -- 10 1 count-- overflow -- 11 1 count-- overflow -- RTR[1:0] (E/213) (E/214) (E/215) (E/216) 0 0 1 1 0 1 0 1 1.0 s 65.536 ms 4.0 s 262.14 ms 8.0 s 524.29 ms 16.0 s 1.049 s 64.0 s 16.384 ms 32.0 s 8.192 ms Main Timer Count Rates 500 ns 32.768 ms 2.0 s 131.07 ms 4.0 s 262.14 ms 8.0 s 524.29 ms 333 ns 21.845 ms 1.333 s 87.381 ms 2.667 s 174.76 ms 5.333 s 349.52 ms 21.330 s 5.491 ms (E/16) (E/220) Periodic (RTI) Interrupt Rates 8.192 ms 16.384 ms 32.768 ms 65.536 ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 2.731 ms 5.461 ms 10.923 ms 21.845 ms CR[1:0] (E/215) (E/217) (E/219) (E/221) 0 0 1 1 0 1 0 1 COP Watchdog Timeout Rates 32.768 ms 131.072 ms 524.288 ms 2.097 s 16.384 ms 65.536 ms 262.14 ms 1.049 s 10.923 ms 43.691 ms 174.76 ms 699.05 ms (E/215) Timeout tolerance (0 ms/+...) 32.8 ms 16.4 ms 10.9 ms MOTOROLA M68HC11E Series Programming Reference Guide 3 M68HC11ERG/AD Interrupt Vector Assignments Vector Address FFC0, C1 FFD4, D5 Reserved SCI serial system(1) SCI receive data register full SCI receiver overrun SCI transmit data register empty SCI transmit complete SCI idle line detect SPI serial transfer complete Pulse accumulator input edge Pulse accumulator overflow Timer overflow Timer input capture 4/output compare 5 Timer output compare 4 Timer output compare 3 Timer output compare 2 Timer output compare 1 Timer input capture 3 Timer input capture 2 Timer input capture 1 Real-time interrupt IRQ (external pin) XIRQ pin Software interrupt Illegal opcode trap COP failure Clock monitor fail RESET Interrupt Source CCR Mask Bit -- Local Mask -- RIE RIE TIE TCIE ILIE SPIE PAII PAOVI TOI I4/O5I OC4I OC3I OC2I OC1I IC3I IC2I IC1I RTII None None None None NOCOP CME None FFD6, D7 I FFD8, D9 FFDA, DB FFDC, DD FFDE, DF FFE0, E1 FFE2, E3 FFE4, E5 FFE6, E7 FFE8, E9 FFEA, EB FFEC, ED FFEE, EF FFF0, F1 FFF2, F3 FFF4, F5 FFF6, F7 FFF8, F9 FFFA, FB FFFC, FD FFFE, FF I I I I I I I I I I I I I I X None None None None None 1. Interrupts generated by SCI; read SCSR to determine source. Refer to HPRIO register to determine priority of interrupt. 4 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Memory Maps M68HC11E Series Memory Maps $0000 EXT $1000 EXT 0000 512 BYTES RAM 01FF 1000 103F 64-BYTE REGISTER BLOCK $B600 EXT EXT BF00 BFFF $D000 BOOT ROM BFC0 BFFF SPECIAL MODES INTERRUPT VECTORS FFC0 $FFFF EXPANDED BOOTSTRAP SPECIAL TEST FFFF NORMAL MODES INTERRUPT VECTORS Figure 1. Memory Map for MC68HC11E0 $0000 EXT $1000 EXT EXT EXT 0000 512 BYTES RAM 01FF 1000 103F 64-BYTE REGISTER BLOCK B600 $B600 EXT EXT BFFF $D000 FFC0 FFFF EXPANDED BOOTSTRAP SPECIAL TEST B7FF BF00 512 BYTES EEPROM BOOT ROM BFC0 BFFF SPECIAL MODES INTERRUPT VECTORS $FFFF NORMAL MODES INTERRUPT VECTORS Figure 2. Memory Map for MC68HC11E1 MOTOROLA M68HC11E Series Programming Reference Guide 5 M68HC11ERG/AD $0000 EXT $1000 EXT EXT EXT 0000 512 BYTES RAM 01FF 1000 103F 64-BYTE REGISTER BLOCK B600 $B600 EXT EXT B7FF BF00 BFFF $D000 D000 512 BYTES EEPROM BOOT ROM BFC0 BFFF SPECIAL MODES INTERRUPT VECTORS 12 KBYTES ROM/EPROM FFC0 NORMAL MODES INTERRUPT VECTORS $FFFF SINGLE CHIP EXPANDED BOOTSTRAP SPECIAL TEST FFFF FFFF Figure 3. Memory Map for MC68HC(7)11E9 $0000 EXT $1000 EXT $9000 EXT $B600 EXT EXT EXT EXT EXT 0000 768 BYTES RAM 02FF 1000 103F 9000 AFFF B600 B7FF BF00 BFFF BOOT ROM BFC0 SPECIAL MODES INTERRUPT VECTORS BFFF 512 BYTES EEPROM 8 KBYTES ROM/EPROM * 64-BYTE REGISTER BLOCK $D000 D000 12 KBYTES ROM/EPROM * FFC0 FFFF FFFF NORMAL MODES INTERRUPT VECTORS $FFFF SINGLE BOOTSTRAP SPECIAL EXPANDED CHIP TEST * 20 Kbytes ROM/EPROM are contained in two segments of 8 Kbytes and 12 Kbytes each. Figure 4. Memory Map for MC68HC(7)11E20 6 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Memory Maps $0000 EXT $1000 EXT 0000 256 BYTES RAM 00FF 1000 103F 64-BYTE REGISTER BLOCK EXT EXT BF00 BFFF BOOT ROM BFC0 SPECIAL MODES INTERRUPT BFFF VECTORS 2048 BYTES EEPROM $F800 F800 FFC0 FFFF NORMAL MODES INTERRUPT VECTORS $FFFF SINGLE CHIP EXPANDED BOOTSTRAP SPECIAL TEST FFFF Figure 5. Memory Map for MC68HC811E2 MOTOROLA M68HC11E Series Programming Reference Guide 7 Opcode Maps 8 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD Page 1 DIR ACCA INH MSB LSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0 TEST NOP IDIV EDIV LSRD ASLD TAP TPA INX DEX CLV SEV CLC SEC CLI SEI 0 INH 0001 1 SBA CBA BRSET BRCLR BSET BCLR TAB TBA PAGE 2 DAA PAGE 3 ABA BSET BCLR BRSET BRCLR 1 REL 0010 2 BRA BRN BHI BLS BCC BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE 2 INH 0011 3 TSX INS PULA PULB DES TXS PSHA PSHB PULX RTS ABX RTI PSHX MUL WAI SWI 3 4 5 CLR 6 7 INC TST JMP XGDX 8 9 BSR LDS STS A B STOP C D CPX JSR PAGE 4 ROR ASR ASL ROL DEC STA EOR ADC ORA ADD COM LSR SUBD AND BIT LDA ACCA 0100 4 ACCB 0101 5 NEG IND,X 0110 6 EXT 0111 7 IMM 1000 8 DIR 1001 9 IND,X 1010 A EXT 1011 B SUB CMP SBC IMM 1100 C ACCB DIR 1101 D IND,X 1110 E EXT 1111 F 0 1 2 ADDD 3 4 5 6 STA 7 8 9 A B LDD STD LDX STX E F C D E F IND,X Page 2 (18XX) MOTOROLA M68HC11E Series Programming Reference Guide 9 ACCA INH MSB LSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 BSET BCLR BRSET BRCLR 1 2 3 4 5 PSHY INC TST JMP CLR 6 7 XGDY 8 9 CPY JSR LDS STS A B C D INY DEY ABY PULY TYS ROR ASR ASL RDL DEC COM LSR 0000 0 0001 1 0010 2 INH 0011 3 TSY 0100 4 0101 5 IND,Y 0110 6 NEG 0111 7 IMM 1000 8 DIR 1001 9 IND,X 1010 A SUB CMP SBC SUBD AND BIT LDA STA EOR ADC ORA ADD EXT 1011 B IMM 1100 C ACCB DIR 1101 D IND,X 1110 E SUB CMP SBC ADDD AND BIT LDA STA EOR ADC ORA ADD LDD STD LDY STY E F EXT 1111 F 0 1 2 3 4 5 6 7 8 9 A B C D E F M68HC11ERG/AD Opcode Maps IND,Y Page 3 (1AXX) 10 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD ACCA IMM MSB LSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D CPY CPD 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 DIR 1001 9 IND,X 1010 A EXT 1011 B 1100 C ACCB IND,X 1101 D 1110 E 1111 F 0 1 2 3 4 5 6 7 8 9 A B C D LDY STY E F E F Page 4 (CDXX) MOTOROLA M68HC11E Series Programming Reference Guide 11 ACCA IND,Y MSB LSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D CPX CPD 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C ACCB IND,Y 1101 D 1110 E 1111 F 0 1 2 3 4 5 6 7 8 9 A B C D LDX STX E F E F M68HC11ERG/AD Opcode Maps M68HC11ERG/AD Simple Branches Mnemonic BRA BRN BSR Opcode 20 21 8D Cycles 3 3 7 Simple Conditional Branches Test N=1 Z=1 V=1 C=1 True Instruction BMI BEQ BVS BCS Opcode 2B 27 29 25 Instruction BPL BNE BVC BCC False Opcode 2A 26 28 24 Signed Conditional Branches Test r>m rm r=m rm r<m True Instruction BGT BGE BEQ BLE BLT Opcode 2E 2C 27 2F 2D Instruction BLE BLT BNE BGT BGE False Opcode 2F 2D 26 2E 2C Unsigned Conditional Branches Test r>m rm r=m rm r<m True Instruction BHI BHS/BCC BEQ BLS BLO/BCS Opcode 22 24 27 23 25 Instruction BLS BL0/BCS BNE BHI BHS/BCC False Opcode 23 25 26 22 24 Bit Manipulation Branches BRCLR Branch if all selected bits are clear (opcode) (operand addr) (mask) (rel offset) M mm = 0? M = operand in memory; mm = mask BRSET Branch if all selected bits are set (opcode) (operand addr) (rel offset) (M) mm = 0? M = operand in memory; mm = mask 12 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD Instruction Set Instruction Set Refer to Table 1, which shows all the M68HC11 instructions in all possible addressing modes. For each instruction, the table shows the operand construction, the number of machine code bytes, and execution time in CPU E-clock cycles. Table 1. Instruction Set (Sheet 1 of 8) Mnemonic ABA ABX ABY ADCA (opr) Operation Add Accumulators Add B to X Add B to Y Add with Carry to A Description A+BA IX + (00 : B) IX IY + (00 : B) IY A+M+CA A A A A A B B B B B A A A A A B B B B B Addressing Mode INH INH INH IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y A A A A A B B B B B IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y EXT IND,X IND,Y A C b7 b0 0 Instruction Opcode 1B 3A 18 3A 89 99 B9 A9 A9 C9 D9 F9 E9 E9 8B 9B BB AB AB CB DB FB EB EB C3 D3 F3 E3 E3 84 94 B4 A4 A4 C4 D4 F4 E4 E4 78 68 68 48 Operand -- -- -- ii dd hh ll ff ff ii dd hh ll ff ff ii dd hh ll ff ff ii dd hh ll ff ff jj kk dd hh ll ff ff ii dd hh ll ff ff ii dd hh ll ff ff hh ll ff ff -- Cycles 2 3 4 2 3 4 4 5 2 3 4 4 5 2 3 4 4 5 2 3 4 4 5 4 5 6 6 7 2 3 4 4 5 2 3 4 4 5 6 6 7 2 S -- -- -- -- X -- -- -- -- Condition Codes H -- -- I -- -- -- -- N -- -- Z -- -- V -- -- C -- -- 18 ADCB (opr) Add with Carry to B B+M+CB -- -- -- 18 ADDA (opr) Add Memory to A A+MA -- -- -- 18 ADDB (opr) Add Memory to B B+MB -- -- -- 18 ADDD (opr) Add 16-Bit to D D + (M : M + 1) D -- -- -- -- 18 ANDA (opr) AND A with Memory AMA -- -- -- -- 0 -- 18 ANDB (opr) AND B with Memory BMB -- -- -- -- 0 -- 18 ASL (opr) Arithmetic Shift Left C b7 b0 -- -- -- -- 0 18 ASLA Arithmetic Shift Left A Arithmetic Shift Left B C b7 b0 INH -- -- -- -- ASLB B 0 INH 58 -- 2 -- -- -- -- ASLD Arithmetic Shift Left D C b7 A b0 b7 B b0 INH 0 05 -- 3 -- -- -- -- MOTOROLA M68HC11E Series Programming Reference Guide 13 M68HC11ERG/AD Table 1. Instruction Set (Sheet 2 of 8) Mnemonic ASR Operation Arithmetic Shift Right b7 b0 C Description Addressing Mode EXT IND,X IND,Y A INH Instruction Opcode 77 67 67 47 Operand hh ll ff ff -- Cycles 6 6 7 2 S -- X -- Condition Codes H -- I -- N Z V C 18 ASRA Arithmetic Shift Right A b7 b0 C -- -- -- -- ASRB Arithmetic Shift Right B b7 b0 C B INH 57 -- 2 -- -- -- -- BCC (rel) BCLR (opr) (msk) BCS (rel) BEQ (rel) BGE (rel) BGT (rel) BHI (rel) BHS (rel) BITA (opr) Branch if Carry Clear Clear Bit(s) ?C=0 M (mm) M REL DIR IND,X IND,Y REL REL REL REL REL REL A A A A A B B B B B IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y REL REL REL REL REL REL REL REL DIR IND,X IND,Y REL DIR IND,X IND,Y DIR IND,X IND,Y REL REL 24 15 1D 1D 25 27 2C 2E 22 24 85 95 B5 A5 A5 C5 D5 F5 E5 E5 2F 25 23 2D 2B 26 2A 20 13 1F 1F 21 12 1E 1E 14 1C 1C 8D 28 rr dd mm ff mm ff mm rr rr rr rr rr rr ii dd hh ll ff ff ii dd hh ll ff ff rr rr rr rr rr rr rr rr dd mm rr ff mm rr ff mm rr rr dd mm rr ff mm rr ff mm rr dd mm ff mm ff mm rr rr 3 6 7 8 3 3 3 3 3 3 2 3 4 4 5 2 3 4 4 5 3 3 3 3 3 3 3 3 6 7 8 3 6 7 8 6 7 8 6 3 -- -- -- -- -- -- -- -- -- -- -- 0 -- -- 18 Branch if Carry Set Branch if = Zero Branch if Zero Branch if > Zero Branch if Higher Branch if Higher or Same Bit(s) Test A with Memory ?C=1 ?Z=1 ?NV=0 ? Z + (N V) = 0 ?C+Z=0 ?C=0 AM -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- 18 BITB (opr) Bit(s) Test B with Memory BM -- -- -- -- 0 -- 18 BLE (rel) BLO (rel) BLS (rel) BLT (rel) BMI (rel) BNE (rel) BPL (rel) BRA (rel) BRCLR(opr) (msk) (rel) BRN (rel) BRSET(opr) (msk) (rel) BSET (opr) (msk) BSR (rel) BVC (rel) Branch if Zero Branch if Lower Branch if Lower or Same Branch if < Zero Branch if Minus Branch if not = Zero Branch if Plus Branch Always Branch if Bit(s) Clear Branch Never Branch if Bit(s) Set Set Bit(s) ? Z + (N V) = 1 ?C=1 ?C+Z=1 ?NV=1 ?N=1 ?Z=0 ?N=0 ?1=1 ? M mm = 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18 ?1=0 ? (M) mm = 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18 M + mm M -- -- -- -- 0 -- 18 Branch to Subroutine Branch if Overflow Clear See Figure 32 ?V=0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 14 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD Instruction Set Table 1. Instruction Set (Sheet 3 of 8) Mnemonic BVS (rel) CBA CLC CLI CLR (opr) Operation Branch if Overflow Set Compare A to B Clear Carry Bit Clear Interrupt Mask Clear Memory Byte Clear Accumulator A Clear Accumulator B Clear Overflow Flag Compare A to Memory Description ?V=1 AB 0C 0I 0M Addressing Mode REL INH INH INH EXT IND,X IND,Y A B INH INH INH A A A A A B B B B B IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y EXT IND,X IND,Y A INH Instruction Opcode 29 11 0C 0E 7F 6F 6F 4F 5F 0A 81 91 B1 A1 A1 C1 D1 F1 E1 E1 73 63 63 43 Operand rr -- -- -- hh ll ff ff -- -- -- ii dd hh ll ff ff ii dd hh ll ff ff hh ll ff ff -- Cycles 3 2 2 2 6 6 7 2 2 2 2 3 4 4 5 2 3 4 4 5 6 6 7 2 S -- -- -- -- -- X -- -- -- -- -- Condition Codes H -- -- -- -- -- I -- -- -- 0 -- N -- -- -- 0 Z -- -- -- 1 V -- -- -- 0 C -- 0 -- 0 18 CLRA CLRB CLV CMPA (opr) 0A 0B 0V AM -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 -- 1 1 -- 0 0 0 0 0 -- 18 CMPB (opr) Compare B to Memory BM -- -- -- -- 18 COM (opr) Ones Complement Memory Byte Ones Complement A Ones Complement B Compare D to Memory 16-Bit $FF M M -- -- -- -- 0 1 18 COMA $FF A A -- -- -- -- 0 1 COMB $FF B B B INH 53 -- 2 -- -- -- -- 0 1 CPD (opr) DM:M +1 IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y INH EXT IND,X IND,Y A INH 1A 1A 1A 1A CD 83 93 B3 A3 A3 8C 9C BC AC AC 8C 9C BC AC AC 19 7A 6A 6A 4A jj kk dd hh ll ff ff jj kk dd hh ll ff ff jj kk dd hh ll ff ff -- hh ll ff ff -- 5 6 7 7 7 4 5 6 6 7 5 6 7 7 7 2 6 6 7 2 -- -- -- -- CPX (opr) Compare X to Memory 16-Bit IX M : M + 1 -- -- -- -- CD 18 18 18 1A 18 CPY (opr) Compare Y to Memory 16-Bit IY M : M + 1 -- -- -- -- DAA DEC (opr) Decimal Adjust A Decrement Memory Byte Decrement Accumulator A Decrement Accumulator B Adjust Sum to BCD M1M -- -- -- -- -- -- -- -- -- 18 DECA A1A -- -- -- -- -- DECB B1B B INH 5A -- 2 -- -- -- -- -- MOTOROLA M68HC11E Series Programming Reference Guide 15 M68HC11ERG/AD Table 1. Instruction Set (Sheet 4 of 8) Mnemonic DES DEX Operation Decrement Stack Pointer Decrement Index Register X Decrement Index Register Y Exclusive OR A with Memory Description SP 1 SP IX 1 IX Addressing Mode INH INH Instruction Opcode 34 09 Operand -- -- Cycles 3 3 S -- -- X -- -- Condition Codes H -- -- I -- -- N -- -- Z -- V -- -- C -- -- DEY IY 1 IY INH 18 09 -- 4 -- -- -- -- -- -- -- EORA (opr) AMA A A A A A B B B B B IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y INH INH EXT IND,X IND,Y 18 88 98 B8 A8 A8 C8 D8 F8 E8 E8 03 02 7C 6C 6C 4C ii dd hh ll ff ff ii dd hh ll ff ff -- -- hh ll ff ff -- 2 3 4 4 5 2 3 4 4 5 41 41 6 6 7 2 -- -- -- -- 0 -- EORB (opr) Exclusive OR B with Memory BMB -- -- -- -- 0 -- 18 FDIV IDIV INC (opr) Fractional Divide 16 by 16 Integer Divide 16 by 16 Increment Memory Byte Increment Accumulator A Increment Accumulator B Increment Stack Pointer Increment Index Register X Increment Index Register Y Jump D / IX IX; r D D / IX IX; r D M+1M -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- 18 INCA A+1A A INH -- -- -- -- -- INCB B+1B B INH 5C -- 2 -- -- -- -- -- INS INX SP + 1 SP IX + 1 IX INH INH 31 08 -- -- 3 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INY IY + 1 IY INH 18 08 -- 4 -- -- -- -- -- -- -- JMP (opr) See Figure 32 EXT IND,X IND,Y DIR EXT IND,X IND,Y A A A A A B B B B B IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y 18 7E 6E 6E 9D BD AD AD 86 96 B6 A6 A6 C6 D6 F6 E6 E6 CC DC FC EC EC hh ll ff ff dd hh ll ff ff ii dd hh ll ff ff ii dd hh ll ff ff jj kk dd hh ll ff ff 3 3 4 5 6 6 7 2 3 4 4 5 2 3 4 4 5 3 4 5 5 6 -- -- -- -- -- -- -- -- JSR (opr) Jump to Subroutine See Figure 32 -- -- -- -- -- -- -- -- 18 LDAA (opr) Load Accumulator A MA -- -- -- -- 0 -- 18 LDAB (opr) Load Accumulator B MB -- -- -- -- 0 -- 18 LDD (opr) Load Double Accumulator D M A,M + 1 B -- -- -- -- 0 -- 18 16 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD Instruction Set Table 1. Instruction Set (Sheet 5 of 8) Mnemonic LDS (opr) Operation Load Stack Pointer Description M : M + 1 SP Addressing Mode IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y EXT IND,X IND,Y A C b7 b0 0 Instruction Opcode 8E 9E BE AE AE CE DE FE EE EE CE DE FE EE EE 78 68 68 48 Operand jj kk dd hh ll ff ff jj kk dd hh ll ff ff jj kk dd hh ll ff ff hh ll ff ff -- Cycles 3 4 5 5 6 3 4 5 5 6 4 5 6 6 6 6 6 7 2 S -- X -- Condition Codes H -- I -- N Z V 0 C -- 18 LDX (opr) Load Index Register X M : M + 1 IX -- -- -- -- 0 -- CD 18 18 18 1A 18 LDY (opr) Load Index Register Y M : M + 1 IY -- -- -- -- 0 -- LSL (opr) Logical Shift Left C b7 b0 -- -- -- -- 0 18 LSLA Logical Shift Left A Logical Shift Left B C b7 b0 INH -- -- -- -- LSLB B 0 INH 58 -- 2 -- -- -- -- LSLD Logical Shift Left Double C b7 A b0 b7 B b0 INH 0 05 -- 3 -- -- -- -- LSR (opr) Logical Shift Right Logical Shift Right A Logical Shift Right B Logical Shift Right Double Multiply 8 by 8 Two's Complement Memory Byte Two's Complement A Two's Complement B No operation OR Accumulator A (Inclusive) 0 b7 b0 C EXT IND,X IND,Y A INH 18 74 64 64 44 hh ll ff ff -- 6 6 7 2 -- -- -- -- 0 LSRA -- -- -- -- 0 0 b7 b0 C LSRB B 0 b7 b0 C INH 54 -- 2 -- -- -- -- 0 LSRD INH 0 b7 A b0 b7 B b0 C 04 -- 3 -- -- -- -- 0 MUL NEG (opr) ABD 0MM INH EXT IND,X IND,Y A INH 3D 70 60 60 40 -- hh ll ff ff -- 10 6 6 7 2 -- -- -- -- -- -- -- -- -- -- -- 18 NEGA 0AA -- -- -- -- NEGB 0BB B INH 50 -- 2 -- -- -- -- NOP ORAA (opr) No Operation A+MA A A A A A B B B B B INH IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y 01 8A 9A BA AA AA CA DA FA EA EA -- ii dd hh ll ff ff ii dd hh ll ff ff 2 2 3 4 4 5 2 3 4 4 5 -- -- -- -- -- -- -- -- -- -- -- 0 -- -- 18 ORAB (opr) OR Accumulator B (Inclusive) B+MB -- -- -- -- 0 -- 18 MOTOROLA M68HC11E Series Programming Reference Guide 17 M68HC11ERG/AD Table 1. Instruction Set (Sheet 6 of 8) Mnemonic PSHA PSHB PSHX Operation Push A onto Stack Push B onto Stack Push X onto Stack (Lo First) Push Y onto Stack (Lo First) Pull A from Stack Pull B from Stack Pull X From Stack (Hi First) Pull Y from Stack (Hi First) Rotate Left C b7 b0 Description A Stk,SP = SP 1 A B Stk,SP = SP 1 B IX Stk,SP = SP 2 Addressing Mode INH INH INH Instruction Opcode 36 37 3C Operand -- -- -- Cycles 3 3 4 S -- -- -- X -- -- -- Condition Codes H -- -- -- I -- -- -- N -- -- -- Z -- -- -- V -- -- -- C -- -- -- PSHY IY Stk,SP = SP 2 INH 18 3C -- 5 -- -- -- -- -- -- -- -- PULA PULB PULX SP = SP + 1, A Stk A SP = SP + 1, B Stk B SP = SP + 2, IX Stk INH INH INH 32 33 38 -- -- -- 4 4 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PULY SP = SP + 2, IY Stk INH 18 38 -- 6 -- -- -- -- -- -- -- -- ROL (opr) EXT IND,X IND,Y A INH 18 79 69 69 49 hh ll ff ff -- 6 6 7 2 -- -- -- -- ROLA Rotate Left A C b7 b0 -- -- -- -- ROLB Rotate Left B C b7 b0 B INH 59 -- 2 -- -- -- -- ROR (opr) Rotate Right b7 b0 C EXT IND,X IND,Y A INH 18 76 66 66 46 hh ll ff ff -- 6 6 7 2 -- -- -- -- RORA Rotate Right A b7 b0 C -- -- -- -- RORB Rotate Right B b7 b0 C B INH 56 -- 2 -- -- -- -- RTI RTS SBA SBCA (opr) Return from Interrupt Return from Subroutine Subtract B from A Subtract with Carry from A See Figure 32 See Figure 32 ABA AMCA A A A A A B B B B B INH INH INH IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y INH INH INH 3B 39 10 82 92 B2 A2 A2 C2 D2 F2 E2 E2 0D 0F 0B -- -- -- ii dd hh ll ff ff ii dd hh ll ff ff -- -- -- 12 5 2 2 3 4 4 5 2 3 4 4 5 2 2 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18 SBCB (opr) Subtract with Carry from B BMCB -- -- -- -- 18 SEC SEI SEV Set Carry Set Interrupt Mask Set Overflow Flag 1C 1I 1V -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- 1 1 -- -- 18 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD Instruction Set Table 1. Instruction Set (Sheet 7 of 8) Mnemonic STAA (opr) Operation Store Accumulator A Store Accumulator B Store Accumulator D Stop Internal Clocks Store Stack Pointer Description AM A A A A B B B B Addressing Mode DIR EXT IND,X IND,Y DIR EXT IND,X IND,Y DIR EXT IND,X IND,Y INH DIR EXT IND,X IND,Y DIR EXT IND,X IND,Y DIR EXT IND,X IND,Y A A A A A A A A A A IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y IMM DIR EXT IND,X IND,Y INH INH INH INH INH INH EXT IND,X IND,Y A B INH INH INH Instruction Opcode 97 B7 A7 A7 D7 F7 E7 E7 DD FD ED ED CF 9F BF AF AF DF FF EF EF DF FF EF EF 80 90 B0 A0 A0 C0 D0 F0 E0 E0 83 93 B3 A3 A3 3F 16 06 17 00 07 7D 6D 6D 4D 5D 30 Operand dd hh ll ff ff dd hh ll ff ff dd hh ll ff ff -- dd hh ll ff ff dd hh ll ff ff dd hh ll ff ff ii dd hh ll ff ff ii dd hh ll ff ff jj kk dd hh ll ff ff -- -- -- -- -- -- hh ll ff ff -- -- -- Cycles 3 4 4 5 3 4 4 5 4 5 5 6 2 4 5 5 6 4 5 5 6 5 6 6 6 2 3 4 4 5 2 3 4 4 5 4 5 6 6 7 14 2 2 2 * 2 6 6 7 2 2 3 S -- X -- Condition Codes H -- I -- N Z V 0 C -- 18 STAB (opr) BM -- -- -- -- 0 -- 18 STD (opr) A M, B M + 1 -- -- -- -- 0 -- 18 STOP STS (opr) -- SP M : M + 1 -- -- -- -- -- -- -- -- -- -- -- 0 -- -- 18 STX (opr) Store Index Register X IX M : M + 1 -- -- -- -- 0 -- CD 18 18 1A 18 STY (opr) Store Index Register Y IY M : M + 1 -- -- -- -- 0 -- SUBA (opr) Subtract Memory from A AMA -- -- -- -- 18 SUBB (opr) Subtract Memory from B BMB -- -- -- -- 18 SUBD (opr) Subtract Memory from D DM:M+1D -- -- -- -- 18 SWI TAB TAP TBA TEST TPA TST (opr) Software Interrupt Transfer A to B Transfer A to CC Register Transfer B to A TEST (Only in Test Modes) Transfer CC Register to A Test for Zero or Minus Test A for Zero or Minus Test B for Zero or Minus Transfer Stack Pointer to X See Figure 32 AB A CCR BA Address Bus Counts CCR A M0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- -- -- -- 0 0 -- -- 0 -- -- -- -- -- 0 18 TSTA TSTB TSX A0 B0 SP + 1 IX -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 -- 0 0 -- MOTOROLA M68HC11E Series Programming Reference Guide 19 M68HC11ERG/AD Table 1. Instruction Set (Sheet 8 of 8) Mnemonic TSY TXS TYS WAI XGDX XGDY Cycle * ** Operation Transfer Stack Pointer to Y Transfer X to Stack Pointer Transfer Y to Stack Pointer Wait for Interrupt Exchange D with X Exchange D with Y Description SP + 1 IY IX 1 SP IY 1 SP Stack Regs & WAIT IX D, D IX IY D, D IY Addressing Mode INH INH INH INH INH INH 18 18 18 Instruction Opcode 30 35 35 3E 8F 8F Operand -- -- -- -- -- -- Cycles 4 3 4 ** 3 4 S -- -- -- -- -- -- X -- -- -- -- -- -- Condition Codes H -- -- -- -- -- -- I -- -- -- -- -- -- N -- -- -- -- -- -- Z -- -- -- -- -- -- V -- -- -- -- -- -- C -- -- -- -- -- -- Infinity or until reset occurs 12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total). Operands dd = 8-bit direct address ($0000$00FF) (high byte assumed to be $00) ff = 8-bit positive offset $00 (0) to $FF (255) (is added to index) hh = High-order byte of 16-bit extended address ii = One byte of immediate data jj = High-order byte of 16-bit immediate data kk = Low-order byte of 16-bit immediate data ll = Low-order byte of 16-bit extended address mm = 8-bit mask (set bits to be affected) rr = Signed relative offset $80 (128) to $7F (+127) (offset relative to address following machine code offset byte)) Operators () Contents of register shown inside parentheses Is transferred to Is pulled from stack Is pushed onto stack Boolean AND + Arithmetic addition symbol except where used as inclusive-OR symbol in Boolean formula Exclusive-OR Multiply : Concatenation Arithmetic subtraction symbol or negation symbol (two's complement) Condition Codes -- Bit not changed 0 Bit always cleared 1 Bit always set Bit cleared or set, depending on operation Bit can be cleared, cannot become set 20 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD Special Operations Special Operations JSR, JUMP TO SUBROUTINE MAIN PROGRAM DIRECT RTI, RETURN FROM INTERRUPT INTERRUPT ROUTINE PC 7 SP SP+1 SP+2 SP+3 SP+4 7 SP2 SP1 SP SP+5 0 SP+6 SP+7 SP+8 SP+9 STACK CCR ACCB ACCA IXH IXL IYH IYL RTNH RTNL STACK CCR ACCB ACCA IXH IXL IYH IYL RTNH RTNL 0 $9D = JSR dd RTN NEXT MAIN INSTR. MAIN PROGRAM PC $3B = RTI INDEXED, X $AD = JSR ff RTN NEXT MAIN INSTR. MAIN PROGRAM PC STACK RTNH RTNL INDEXED, Y $18 = PRE $AD = JSR RTN ff NEXT MAIN INSTR. MAIN PROGRAM PC SWI, SOFTWARE INTERRUPT MAIN PROGRAM PC 7 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 7 SP 0 0 $3F = SWI INDEXED, Y $BD = PRE hh RTN ll NEXT MAIN INSTR. PC WAI, WAIT FOR INTERRUPT MAIN PROGRAM PC $3E = WAI BSR, BRANCH TO SUBROUTINE MAIN PROGRAM PC STACK RTNH RTNL $8D = BSR SP2 SP1 SP LEGEND: RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO BE EXECUTED UPON RETURN FROM SUBROUTINE RTNH = MOST SIGNIFICANT BYTE OF RETURN ADDRESS RTNL = LEAST SIGNIFICANT BYTE OF RETURN ADDRESS = STACK POINTER POSITION AFTER OPERATION IS COMPLETE dd = 8-BIT DIRECT ADDRESS ($0000$00FF) (HIGH BYTE ASSUMED TO BE $00) ff = 8-BIT POSITIVE OFFSET $00 (0) TO $FF (255) IS ADDED TO INDEX hh = HIGH-ORDER BYTE OF 16-BIT EXTENDED ADDRESS ll = LOW-ORDER BYTE OF 16-BIT EXTENDED ADDRESS rr = SIGNED RELATIVE OFFSET $80 (128) TO $7F (+127) (OFFSET RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE OFFSET BYTE) RTS, RETURN FROM SUBROUTINE MAIN PROGRAM PC 7 SP SP+1 SP+2 STACK RTNH RTNL 0 $39 = RTS MOTOROLA M68HC11E Series Programming Reference Guide 21 M68HC11ERG/AD M68HC11E Series Registers Figure 6 provides a summary of the M68HC11E registers. Note that the 128-byte register block can be remapped to any 4K boundary. Addr. $1000 $1001 Register Name Read: Port A Data Register (PORTA) Reserved Read: $1002 Parallel I/O Control Register (PIOC) Write: Reset: Read: $1003 Port C Data Register (PORTC) Write: Reset: Read: $1004 Port B Data Register (PORTB) Write: Reset: Read: $1005 $1006 Port C Latched Register (PORTCL) Reserved Read: $1007 Port C Data Direction Register (DDRC) Write: Reset: Read: $1008 Port D Data Register (PORTD) Write: Reset: Read: $1009 Port D Data Direction Register (DDRD) Write: Reset: Read: $100A Port E Data Register (PORTE) Write: Reset: Read: $100B Timer Compare Force Register (CFORC) Write: Reset: FOC1 0 FOC2 FOC3 0 PE7 Write: Reset: R R R PB7 0 PCL7 PB6 PB5 Write: Reset: Bit 7 PA7 I R 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 Bit 0 PA0 0 R 0 R 0 R I R I R I R I R STAF 0 PC7 STAI CWOM HNDS OIN PLS EGA INVB 0 PC6 0 PC5 0 PC4 0 PC3 U PC2 1 PC1 1 PC0 Indeterminate after reset PB4 PB3 PB2 PB1 PB0 0 PCL6 0 PCL5 0 PCL4 0 PCL3 0 PCL2 0 PCL1 0 PCL0 Indeterminate after reset R R R R R DDRC7 0 0 U DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 PD5 0 PD4 0 PD3 0 PD2 0 PD1 0 PD0 U I DDRD5 I DDRD4 I DDRD3 I DDRD2 I DDRD1 I DDRD0 0 PE6 0 PE5 0 PE4 0 PE3 0 PE2 0 PE1 0 PE0 Indeterminate after reset FOC4 FOC5 0 0 0 R 0 = Reserved 0 0 0 = Unimplemented I = Indeterminate after reset U = Unaffected Figure 6. Register and Control Bit Assignments (Sheet 1 of 6) 22 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers Addr. $100C Register Name Read: Output Compare 1 Mask Register (OC1M) Write: Reset: Read: Bit 7 OC1M7 0 OC1D7 0 Bit 15 0 Bit 7 0 Bit 15 6 OC1M6 5 OC1M5 4 OC1M4 3 OC1M3 2 1 Bit 0 0 OC1D6 0 OC1D5 0 OC1D4 0 OC1D3 0 0 0 $100D Output Compare 1 Data Register (OC1D) Write: Reset: Read: 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 $100E Timer Counter Register High (TCNTH) Write: Reset: Read: 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 $100F Timer Counter Register Low (TCNTL) Write: Reset: Read: 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 $1010 Timer Input Capture 1 Register High (TIC1H) Write: Reset: Read: Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $1011 Timer Input Capture 1 Register Low (TIC1L) Write: Reset: Read: Indeterminate after reset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $1012 Timer Input Capture 2 Register High (TIC2H) Write: Reset: Read: Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $1013 TImer Input Capture 2 Register Low (TIC2L) Write: Reset: Read: Indeterminate after reset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $1014 Timer Input Capture 3 Register High (TIC3H) Write: Reset: Read: Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $1015 Timer Input Capture 3 Register Low (TIC3L) Write: Reset: Read: Indeterminate after reset Bit 15 1 Bit 7 1 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $1016 Timer Output Compare 1 Register High (TOC1H) Write: Reset: Read: 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 $1017 Timer Output Compare 1 Register Low (TOC1L) Write: Reset: 1 1 1 R 1 = Reserved 1 1 1 = Unimplemented I = Indeterminate after reset U = Unaffected Figure 6. Register and Control Bit Assignments (Sheet 2 of 6) MOTOROLA M68HC11E Series Programming Reference Guide 23 M68HC11ERG/AD Addr. $1018 Register Name Read: Timer Output Compare 2 Register High (TOC2H) Write: Reset: Read: Bit 7 Bit 15 1 Bit 7 1 Bit 15 1 Bit 7 1 Bit 15 1 Bit 7 1 Bit 15 1 Bit 7 1 OM2 0 EDG4B 0 OC1I 0 OC1F 0 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 $1019 Timer Output Compare 2 Register Low (TOC2L) Write: Reset: Read: 1 Bit 14 1 Bit 13 1 Bit 12 1 Bit 11 1 Bit 10 1 Bit 9 1 Bit 8 Timer Output Compare 3 Register $101A High (TOC3H) Write: Reset: Read: 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 $101B Timer Output Compare 3 Register Low (TOC3L) Write: Reset: Read: 1 Bit 14 1 Bit 13 1 Bit 12 1 Bit 11 1 Bit 10 1 Bit 9 1 Bit 8 $101C Timer Output Compare 4 Register High (TOC4H) Write: Reset: Read: 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 $101D Timer Output Compare 4 Register Low (TOC4L) Write: Reset: 1 Bit 14 1 Bit 13 1 Bit 12 1 Bit 11 1 Bit 10 1 Bit 9 1 Bit 8 $101E Timer Input Capture 4/Output Read: Compare 5 Register High Write: (TI4/O5) Reset: Timer Input Capture 4/Output Read: Compare 5 Register Low Write: (TI4/O5) Reset: Read: Timer Control Register 1 (TCTL1) Write: Reset: Read: 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 $101F 1 OL2 1 OM3 1 OL3 1 OM4 1 OL4 1 OM5 1 OL5 $1020 0 EDG4A 0 EDG1B 0 EDG1A 0 EDG2B 0 EDG2A 0 EDG3B 0 EDG3A $1021 Timer Control Register 2 (TCTL2) Write: Reset: Read: 0 OC2I 0 OC3I 0 OC4I 0 I4/O5I 0 IC1I 0 IC2I 0 IC3I $1022 Timer Interrupt Mask 1 Register (TMSK1) Write: Reset: Read: 0 OC2F 0 OC3F 0 OC4F 0 I4/O5F 0 IC1F 0 IC2F 0 IC3F $1023 Timer Interrupt Flag 1 (TFLG1) Write: Reset: 0 0 0 R 0 = Reserved 0 0 0 = Unimplemented I = Indeterminate after reset U = Unaffected Figure 6. Register and Control Bit Assignments (Sheet 3 of 6) 24 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers Addr. $1024 Register Name Read: Timer Interrupt Mask 2 Register (TMSK2) Write: Reset: Read: Bit 7 TOI 0 TOF 0 DDRA7 0 Bit 7 6 RTII 5 PAOVI 4 PAII 3 2 1 PR1 Bit 0 PR0 0 RTIF 0 PAOVF 0 PAIF 0 0 0 0 $1025 Timer Interrupt Flag 2 (TFLG2) Write: Reset: Read: 0 PAEN 0 PAMOD 0 PEDGE 0 DDRA3 0 I4/O5 0 RTR1 0 RTR0 $1026 Pulse Accumulator Control Register (PACTL) Write: Reset: Read: 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 $1027 Pulse Accumulator Count Register (PACNT) Write: Reset: Read: Indeterminate after reset SPIE 0 SPIF 0 Bit 7 SPE DWOM MSTR CPOL CPHA SPR1 SPR0 $1028 Serial Peripheral Control Register (SPCR) Write: Reset: Read: 0 WCOL 0 0 MODF 0 1 U U $1029 Serial Peripheral Status Register (SPSR) Write: Reset: Read: 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 $102A Serial Peripheral Data I/O Register (SPDR) Write: Reset: Read: Indeterminate after reset TCLR 0 R8 I TIE 0 TDRE 1 SCP2(1) SCP1 SCP0 RCKB SCR2 SCR1 SCR0 $102B Baud Rate Register (BAUD) Write: Reset: Read: 0 T8 0 0 M 0 WAKE U U U $102C Serial Communications Control Register 1 (SCCR1) Write: Reset: Read: I TCIE 0 RIE 0 ILIE 0 TE 0 RE 0 RWU 0 SBK $102D Serial Communications Control Register 2 (SCCR2) Write: Reset: Read: 0 TC 0 RDRF 0 IDLE 0 OR 0 NF 0 FE 0 $102E Serial Communications Status Register (SCSR) Write: Reset: Read: 1 0 0 0 0 0 0 1. SCP2 adds 39 to SCI prescaler and is present only in MC68HC(7)11E20. $102F Serial Communications Data Register (SCDR) Write: Reset: = Unimplemented I = Indeterminate after reset R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0 Indeterminate after reset R = Reserved U = Unaffected Figure 6. Register and Control Bit Assignments (Sheet 4 of 6) MOTOROLA M68HC11E Series Programming Reference Guide 25 M68HC11ERG/AD Addr. $1030 Register Name Read: Analog-to-Digital Control Status Register (ADCTL) Write: Reset: Read: Bit 7 CCF 0 Bit 7 6 5 SCAN 4 MULT 3 CD 2 CC 1 CB Bit 0 CA 0 Bit 6 Bit 5 Bit 4 Indeterminate after reset Bit 3 Bit 2 Bit 1 Bit 0 Analog-to-Digital Results Register $1031 1 (ADR1) Write: Reset: Read: Bit 7 Bit 6 Bit 5 Indeterminate after reset Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $1032 Analog-to-Digital Results Register 2 (ADR2) Write: Reset: Read: Bit 7 Bit 6 Bit 5 Indeterminate after reset Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Analog-to-Digital Results Register $1033 3 (ADR3) Write: Reset: Read: Bit 7 Bit 6 Bit 5 Indeterminate after reset Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $1034 Analog-to-Digital Results Register 4 (ADR4) Write: Reset: Read: Indeterminate after reset PTCON 0 MBE 0 R R Read: BPRT3 BPRT2 BPRT1 BPRT0 $1035 Block Protect Register (BPROT) Write: Reset: Read: 0 0 ELAT 1 EXCOL 1 EXROW 1 T1 1 T0 1 PGM $1036 EPROM Programming Control Register (EPROG)(1) Write: Reset: 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 1. MC68HC711E20 only $1037 $1038 Reserved Reserved $1039 System Configuration Options Register (OPTION) Write: Reset: Read: ADPU 0 Bit 7 0 ODD 0 CSEL IRQE(1) DLY(1) CME CR1(1) CR0(1) 0 Bit 6 0 Bit 5 1 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 $103A Arm/Reset COP Timer Circuitry Register (COPRST) Write: Reset: 0 EVEN 0 ELAT(2) 0 BYTE 0 ROW 0 ERASE 0 EELAT 0 EPGM $103B EPROM and EEPROM Read: Programming Control Register Write: (PPROG) Reset: 0 SMOD 0 MDA 0 IRV(NE) 0 PSEL3 0 PSEL2 0 PSEL1 0 PSEL0 $103C Highest Priority I Bit Interrupt and Read: RBOOT Miscellaneous Register Write: (HPRIO) Reset: 0 0 0 0 R 0 = Reserved 1 1 0 = Unimplemented I = Indeterminate after reset U = Unaffected Figure 6. Register and Control Bit Assignments (Sheet 5 of 6) 26 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers Addr. $103D $103E Register Name Read: RAM and I/O Mapping Register (INIT) Reserved Read: Write: Reset: Bit 7 RAM3 0 R 6 RAM2 5 RAM1 4 RAM0 3 REG3 2 REG2 1 REG1 Bit 0 REG0 0 R 0 R 0 R 0 R 0 R 0 R 1 R $103F System Configuration Register (CONFIG) Write: Reset: Read: 0 EE3 1 NOSEC NOCOP ROMON EEON 0 EE2 0 EE1 0 EE0 U NOSEC U NOCOP 1 U EEON $103F System Configuration Register (CONFIG)(3) Write: Reset: 1 1 1 U U 1 1 1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes. 2. MC68HC711E9 only 3. MC68HC811E2 only = Unimplemented I = Indeterminate after reset R = Reserved U = Unaffected Figure 6. Register and Control Bit Assignments (Sheet 6 of 6) A/D Control/Status Register (ADCTL) Address: Read: Write: Reset: 0 0 = Unimplemented $1030 Bit 7 CCF 6 5 SCAN 4 MULT 3 CD 2 CC 1 CB Bit 0 CA Indeterminate after reset CCF -- Conversion Complete Flag This bit is set after an A/D conversion cycle and cleared when ADCTL is written. Bit 6 -- Unimplemented Always reads 0 SCAN -- Continuous Scan Control 0 = Do four conversions and stop 1 = Convert four channels in selected group continuously MULT -- Multiple Channel/Single Channel Control 0 = Convert single channel selected 1 = Convert four channels in selected group CD:CA -- Channel Selects D:A Refer to the following table. MOTOROLA M68HC11E Series Programming Reference Guide 27 M68HC11ERG/AD Channel Select Control Bits CD:CC:CB:CA 0000 0001 0010 0011 0100 0101 0110 0111 10XX 1100 1101 1110 1111 Channel Signal AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved VRH(1) VRL (1) Result in ADRx if MULT = 1 ADR1 ADR2 ADR3 ADR4 ADR1 ADR2 ADR3 ADR4 -- ADR1 ADR2 ADR3 ADR4 Result in ADRx if MULT = 0 ADR[4:1] ADR[4:1] ADR[4:1] ADR[4:1] ADR[4:1] ADR[4:1] ADR[4:1] ADR[4:1] -- ADR[4:1] ADR[4:1] ADR[4:1] ADR[4:1] (VRH)/2(1) Reserved(1) 1. Used for factory testing A/D Results (ADR1ADR4) ADR1 -- Address: $1031 Bit 7 6 5 Read: Bit 7 6 5 Write: Reset: ADR2 -- Address: $1032 Bit 7 6 5 Read: Bit 7 6 5 Write: Reset: ADR3 -- Address: $1033 Bit 7 6 5 Read: Bit 7 6 5 Write: Reset: ADR4 -- Address: $1034 Bit 7 6 5 Read: Bit 7 6 5 Write: Reset: = Unimplemented 4 4 3 3 2 2 1 1 Bit 0 Bit 0 Indeterminate after reset 4 4 3 3 2 2 1 1 Bit 0 Bit 0 Indeterminate after reset 4 4 3 3 2 2 1 1 Bit 0 Bit 0 Indeterminate after reset 4 4 3 3 2 2 1 1 Bit 0 Bit 0 Indeterminate after reset 28 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers Analog Input to 8-Bit Result Translation Table Bit 7 % (1) (2) (3) 6 25% 1.250 8.25 5 12.5% 0.625 0.4125 4 6.25% 0.3125 0.2063 3 3.12% 0.1562 0.1031 2 1.56% 0.0781 0.0516 1 0.78% 0.0391 0.0258 Bit 0 0.39% 0.0195 0.0129 50% 2.500 1.65 Volts Volts 1. % of VRHVRL 2. Voltages for VRL = 0; VRH = 5.0 V 3. Voltages for VRL = 0; VRH = 3.3 V Baud Rate Control Register (BAUD) Address: $102B Bit 7 Read: Write: Reset: TCLR 0 U = Unaffected 6 SCP2 0 5 SCP1 0 4 SCP0 0 3 RCKB 0 2 SCR2 U 1 SCR1 U Bit 0 SCR0 U TCLR -- Clear Baud Rate Counter (Test) SCP[2:0] -- SCI Baud Rate Prescaler Select SCP2 applies to the MC68HC(7)11E20 only. When SCP2 = 1, SCP[1:0] must equal 0. Any other values for SCP[1:0] are not decoded in the prescaler and the results are unpredictable. SCP 2(1) 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 Divide Internal Clock By 1 3 4 13 39 Crystal Frequency (MHz) 4.0 62500 20833 15625 4800 1602 4.9152 76800 25600 19200 5907 1969 8.0 125000 41667 31250 9600 3205 8.3886 131072 43691 32768 10082 3361 12.0 187500 62500 46875 14423 4808 1. Shaded areas apply to MC68HC(7)11E20 only. RCKB -- SCI Baud Rate Clock Check (TEST) MOTOROLA M68HC11E Series Programming Reference Guide 29 M68HC11ERG/AD SCR[2:0] -- SCI Baud Rate Selects Selects receiver and transmitter bit rate based on output from baud rate prescaler stage. Refer to SCI baud rate generator block diagram. SCR 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 Divide Prescaler By 1 2 4 8 16 32 64 128 Highest Baud Rate (Prescaler Output from Previous Table 131072 76800 32768 19200 131072 76800 32768 19200 65536 38400 16384 9600 32768 19200 8192 4800 16384 9600 4096 2400 8192 480 2048 1200 4096 2400 1024 600 2048 1200 512 300 1024 600 256 150 4800 4800 2400 1200 600 300 150 75 37.5 Block Protect Register (BPROT) Address: Read: Write: Reset: $1035 Bit 7 6 5 4 PTCON 0 0 0 = Unimplemented 1 3 BPRT3 1 2 BPRT2 1 1 BPRT1 1 Bit 0 BPRT0 1 Bits [7:5] -- Unimplemented Always read 0 PTCON -- Protect CONFIG Register 0 = CONFIG register can be programmed or erased normally. 1 = CONFIG register cannot be programmed or erased. BPRT[3:0] -- Block Protect for EEPROM Block protect register bits can be written to 0 (protection disabled) only once within 64 cycles of a reset in normal modes, or at any time in special modes. Block protect register bits can be written to 1 (protection enabled) at any time. 0 = Protection disabled for associated block 1 = Protection enabled for associated block Bit Name BPRT0 BPRT1 BPRT2 BPRT3 BPRT0 BPRT1 BPRT2 BPRT3 Block Protected $B600$B61F $B620$B65F $B660$B6DF $B6E0$B7FF MC68HC811E2 Only $x800$x9FF(1) $xA00$xBFF(1) $xC00$xDFF $xE00$xFFF (1) (1) Block Size 32 bytes 64 bytes 128 bytes 288 bytes 512 bytes 512 bytes 512 bytes 512 bytes 1. x is determined by the value of EE[3:0] in CONFIG (MC68HC811E2 only). Refer to the MC68HC811E2 CONFIG register. 30 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers Timer Compare Force Register (CFORC) Address: Read: Write: Reset: $100B Bit 7 FOC1 0 6 FOC2 0 = Unimplemented 5 FOC3 0 4 FOC4 0 3 FOC5 0 0 0 0 2 1 Bit 0 FOC[1:5] -- Force Output Comparison Write 1s to force compare(s). 0 = Not affected 1 = Output x action occurs Bits [2:0] -- Unimplemented Always read 0 Configuration Register (CONFIG) Security disable, COP, ROM mapping, and EEPROM enables Address: Read: Write: Resets: Single chip: Bootstrap: Expanded: Test: 0 0 0 0 0 0 0 0 = Unimplemented U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset, but the function of COP is controlled by the DISR bit in TEST1 register. 0 0 0 0 0 0 0 0 $103F Bit 7 6 5 4 3 NOSEC 2 NOCOP 1 ROMON Bit 0 EEON U U 1 1 U U(L) U U(L) 1 U U U U U U U The following register description applies to the MC68HC11E2 only. Address: Read: Write: Resets: Single chip: Bootstrap: Expanded: Test: $103F Bit 7 EE3 6 EE2 5 EE1 4 EE0 3 NOSEC 2 NOCOP 1 Bit 0 EEON 1 1 U U 1 1 U U = Unimplemented 1 1 U U 1 1 U U U U 1 1 U U(L) U U(L) 1 1 1 1 1 1 U 0 U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset, but the function of COP is controlled by the DISR bit in TEST1 register. MOTOROLA M68HC11E Series Programming Reference Guide 31 M68HC11ERG/AD EE[3:0] -- EEPROM Map Position (MC68HC811E2 only) EE[3:0] determine the upper four bits of EEPROM address, positioning EEPROM at the selected 4-Kbyte boundary. In single-chip and boot modes, these bits are set to 1s during reset and EEPROM is mapped to top of memory. Not implemented in other E-series devices; always read 0. Refer to the following table. EE3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 EE1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 EE2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 EE0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 EEPROM Location $0800$0FFF $1800$1FFF $2800$2FFF $3800$3FFF $4800$4FFF $5800$5FFF $6800$6FFF $7800$7FFF $8800$8FFF $9800$9FFF $A800$AFFF $B800$BFFF $C800$CFFF $D800$DFFF $E800$EFFF $F800$FFFF NOSEC -- Security Disable NOSEC is invalid unless the security mask option is specified before the MCU is manufactured. If the security mask option is omitted NOSEC always reads 1. The enhanced security feature is available in the MC68S711E9 MCU. The enhancement to the standard security feature protects the EPROM as well as RAM and EEPROM. 0 = RAM/EEPROM security mode enabled 1 = RAM/EEPROM security mode disabled NOCOP -- COP System Disable Resets to programmed value. 0 = COP enabled (forces reset on timeout) 1 = COP disabled (does not force reset on timeout) ROMON -- ROM/EPROM Enable In single-chip mode, ROMON is forced to 1 out of reset. ROMON does not apply to the MC68HC811E2. For devices with disabled ROM arrays (the MC68HC11E0, MC68HC11E1, MC68L11E0, or MC68L11E1) ROMON must never be set to 1. 0 = ROM/EPROM removed from the memory map 1 = ROM/EPROM present in the memory map EEON -- EEPROM Enable 0 = EEPROM removed from the memory map 1 = EEPROM present in the memory map 32 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers Arm/Reset COP Timer Circuitry Register (COPRST) Address: Read: Write: Reset: $103A Bit 7 BIT 7 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 BIT 0 0 Write $55 to COPRST to arm COP watchdog clearing mechanism. Write $AA to COPRST to reset COP watchdog. Data Direction Register for Port C (DDRC) Address: Read: Write: Reset: $1007 Bit 7 DDC7 0 6 DDC6 0 5 DDC5 0 4 DDC4 0 3 DDC3 0 2 DDC2 0 1 DDC1 0 Bit 0 DDC0 0 DDC[7:0] -- Data Direction for Port C In handshake output mode, DDRC bits selected the three-stated output option (DDCx = 1). 0 = Input 1 = Output Data Direction Register for Port D (DDRD) Address: Read: Write: Reset: 0 0 Unimplemented $1009 Bit 7 6 5 DDD5 0 4 DDD4 0 3 DDD3 0 2 DDD2 0 1 DDD1 0 Bit 0 DDD0 0 Bits [7:6] -- Unimplemented Always read 0 DDD[5:0] -- Data Direction for Port D 0 = Input 1 = Output EPROM Programming Control Register (EPROG) Address: Read: Write: Reset: $1036 Bit 7 MBE 0 0 = Unimplemented 6 5 ELAT 0 4 EXCOL 0 3 EXROW 0 2 T1 0 1 T0 0 Bit 0 PGM 0 MOTOROLA M68HC11E Series Programming Reference Guide 33 M68HC11ERG/AD NOTE: EPROG is present only on the MC68HC711E20. MBE -- Multiple-Byte Programming Enable When multiple-byte programming is enabled, address bit 5 is considered a don't care so that bytes with address bit 5 = 0 and address bit 5 = 1 both get programmed. MBE can be read in any mode and always reads 0 in normal modes. MBE can be written only in special modes. 0 = EPROM array configured for normal programming 1 = Program two bytes with the same data Bit 6 -- Unimplemented Always reads 0 ELAT -- EPROM/OTPROM Latch Control When ELAT = 1, writes to EPROM cause address and data to be latched and the EPROM/OTPROM cannot be read. ELAT can be read any time. ELAT can be written any time except when PGM = 1; then the write to ELAT is disabled. 0 = EPROM/OTPROM address and data bus configured for normal reads 1 = EPROM/OTPROM address and data bus configured for programming EXCOL -- Select Extra Columns 0 = User array selected 1 = User array is disabled and extra columns are accessed at bits [7:0]. Addresses use bits [13:5] and bits [4:0] are don't care. EXCOL can be read and written only in special modes and always returns 0 in normal modes. EXROW -- Select Extra Rows 0 = User array selected 1 = User array is disabled and two extra rows are available. Addresses use bits [7:0] and bits [13:8] are don't care. EXROW can be read and written only in special modes and always returns 0 in normal modes. T[1:0] -- EPROM Test Mode Select These bits allow selection of either gate stress or drain stress test modes. They can be read and written only in special modes and always read 0 in normal modes. T1 0 0 1 1 T0 0 1 0 1 Function Selected Normal mode Reserved Gate stress Drain stress PGM -- EPROM Programming Voltage Enable PGM can be read any time and can be written only when ELAT = 1. 0 = Programming voltage to EPROM array disconnected 1 = Programming voltage to EPROM array connected 34 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers Highest Priority I Bit Interrupt and Miscellaneous (HPRIO) Address: $103C Bit 7 Read: RBOOT(1) Write: 6 SMOD(1) 5 MDA(1) 4 IRVNE 3 PSEL3 2 PSEL2 1 PSEL1 Bit 0 PSEL0 Reset: 0 0 0 0 Single chip: 0 1 0 0 Expanded: 0 0 1 1 Bootstrap: 1 1 1 0 Special test: 1. The values of the RBOOT, SMOD, and MDA reset bits RESET pin rising edge. 0 0 0 0 depend on 1 1 1 1 the mode 0 1 0 1 0 1 0 1 selected at the RBOOT -- Read Bootstrap ROM Valid only when SMOD is set to 1 (bootstrap or special test mode). Can only be written in special modes. 0 = Bootloader ROM disabled and not in map 1 = Bootloader ROM enabled and in map at $BE00$BFFF SMOD and MDA -- Special Mode Select and Mode Select A The initial value of SMOD is in the inverse of the logic level present on the MODB pin at the rising edge of reset. The initial value of MDA equals the logic level present on the MODA pin at the rising edge of reset. These two bits can be read at any time. They can be written anytime in special modes. MDA can only be written once in normal modes. SMOD cannot be set once it has been cleared. Refer to the following table. Inputs MODB 1 1 0 0 MODA 0 1 0 1 Mode Single chip Expanded Bootstrap Special test Latched at Reset SMOD MDA 0 0 0 1 1 0 1 1 IRVNE -- Internal Read Visibility/Not E (IRV in MC68HC811E2) IRVNE can be written once in any mode. In expanded modes, IRVNE determines whether IRV is on or off. In special test mode, IRVNE is reset to 1. For the MC68HC811E2, this bit controls only internal read visibility function and has no meaning or effect in single-chip modes. 0 = No internal read visibility on external bus 1 = Data from internal reads is driven out the external data bus In single-chip modes this bit determines whether the E clock drives out from the chip. 0 = E is driven out from the chip. 1 = E pin is driven low. Refer to the following table. Mode Single chip Expanded Bootstrap Special test IRVNE Out of Reset 0 0 0 1 E Clock Out of Reset On On On On IRV Out of Reset Off Off Off On IRVNE Affects Only E IRV E IRV IRVNE Can Be Written Once Once Once Once MOTOROLA M68HC11E Series Programming Reference Guide 35 M68HC11ERG/AD NOTE: When IRV function is used, care must be taken to ensure that bus conflicts do not occur. Data can be driven onto the bus even though the R/W line indicates a high-impedance state on data bus pins. PSEL[3:0] -- Priority Select Can be written only while bit I in the CCR is set (interrupts disabled). These bits select one interrupt source to be elevated above all other I bit related sources. Refer to the following table. PSEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PSEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PSEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PSEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Interrupt Source Promoted Timer overflow Pulse accumulator overflow Pulse accumulator input edge SPI serial transfer complete SCI serial system Reserved (default to IRQ) IRQ (external pin or parallel I/O) Real-time interrupt Timer input capture 1 Timer input capture 2 Timer input capture 3 Timer output compare 1 Timer output compare 2 Timer output compare 3 Timer output compare 4 Timer input capture 4/output compare 5 RAM and Register Mapping (INIT) Address: Read: Write: Reset: $103D Bit 7 RAM3 0 6 RAM2 0 5 RAM1 0 4 RAM0 0 3 REG3 0 2 REG2 0 1 REG1 0 Bit 0 REG0 1 RAM[3:0] -- Internal RAM Map Position Determine the upper four bits of RAM address. At reset, RAM is mapped to $0000. RAM[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Address $0000$0xFF $1000$1xFF $2000$2xFF $3000$3xFF $4000$4xFF $5000$5xFF $6000$6xFF $7000$7xFF RAM[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Address $8000$8xFF $9000$9xFF $A000$AxFF $B000$BxFF $C000$CxFF $D000$DxFF $E000$ExFF $F000$FxFF 36 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers REG[3:0] -- 64-Byte Register Block Map Position Determine upper four bits of register space address. At reset, registers are mapped to $1000. REG[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Address $0000$003F $1000$103F $2000$203F $3000$303F $4000$403F $5000$503F $6000$603F $7000$703F REG[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Address $8000$803F $9000$903F $A000$A03F $B000$B03F $C000$C03F $D000$D03F $E000$E03F $F000$F03F NOTE: Can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes. Output Compare 1 Data Register (OC1D) Address: $100D Bit 7 Read: Write: Reset: OC1D7 0 6 OC1D6 0 Unimplemented 5 OC1D5 0 4 OC1D4 0 3 OC1D3 0 0 0 0 2 1 Bit 0 If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares. Bits [2:0]-- Unimplemented Always reads 0 Output Compare 1 Mask Register (OC1M) Address: $100C Bit 7 Read: Write: Reset: OC1M7 0 6 OC1M6 0 Unimplemented 5 OC1M5 0 4 OC1M4 0 3 OC1M3 0 0 0 0 2 1 Bit 0 OC1M[7:3] -- Output Compare Masks 0 = OC1 disabled 1 = OC1 enabled to control the corresponding pin of port A Bits [2:0]-- Unimplemented Always reads 0 MOTOROLA M68HC11E Series Programming Reference Guide 37 M68HC11ERG/AD System Configuration Options (OPTION) Address: Read: Write: Reset: $1039 Bit 7 ADPU 0 6 CSEL 0 5 IRQE(1) 0 4 DLY(1) 1 3 CME 0 0 2 1 CR1(1) 0 Bit 0 CR0(1) 0 1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes. = Unimplemented ADPU -- Analog-to-Digital (A/D) Converter Power-Up 0 = A/D powered down 1 = A/D powered up CSEL -- Clock Select 0 = A/D and EEPROM charge pumps use system E clock 1 = A/D and EEPROM charge pumps use internal RC oscillator IRQE -- IRQ Select Edge-Sensitive Only 0 = Low level recognition 1 = Falling edge recognition DLY -- Enable Oscillator Startup Delay on Exit from Stop Mode 0 = No stabilization delay on exit from stop mode 1 = Stabilization delay enabled on exit from stop mode CME -- Clock Monitor Enable 0 = Clock monitor disabled; slow clocks can be used 1 = Slow or stopped clocks cause clock failure reset Bit 2 -- Not implemented Always reads 0 CR[1:0] -- COP Timer Rate Select Refer to the following table. CR[1:0] 00 01 10 11 Divide E/2 15 By XTAL = 4.0 MHz Timeout 0 ms, + 32.8 ms 32.768 ms 131.072 ms 524.28 ms 2.098 s 1.0 MHz XTAL = 8.0 MHz Timeout 0 ms, + 16.4 ms 16.384 ms 65.536 ms 262.14 ms 1.049 s 2.0 MHz XTAL = 12.0 MHz Timeout 0 ms, + 10.9 ms 10.923 ms 43.691 ms 174.76 ms 699.05 ms 3.0 MHz XTAL = 16.0 MHz Timeout 0 ms, + 8.2 ms 8.19 ms 32.8 ms 131 ms 524 ms 4.0 MHz 1 4 16 64 E= Pulse Accumulator Counter (PACNT) Address: $1027 Bit 7 Read: Write: Reset: BIT 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 BIT 0 Unaffected by reset 38 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers Pulse Accumulator Control (PACTL) Address: $1026 Bit 7 Read: Write: Reset: DDRA7 0 6 PAEN 0 5 PAMOD 0 4 PEDGE 0 3 DDRA3 0 2 I4/O5 0 1 RTR1 0 Bit 0 RTR0 0 DDRA7 -- Data Direction for Port A Bit 7 0 = Input only 1 = Output PAEN -- Pulse Accumulator System Enable 0 = Pulse accumulator disabled 1 = Pulse accumulator enabled PAMOD -- Pulse Accumulator Mode 0 = Event counter 1 = Gated time accumulation PEDGE -- Pulse Accumulator Edge Control Refer to the following table. PAMOD 0 0 1 1 PEDGE 0 1 0 1 Action on Clock PAI falling edge increments the counter. PAI rising edge increments the counter. A zero on PAI inhibits counting. A one on PAI inhibits counting. DDRA3 -- Data Direction for Port A Bit 3 Overridden if an output compare function is configured to control the PA3 pin. 0 = Input 1 = Output I4/O5 -- Input Capture 4/Output Compare 5 Configure TI4/O5 for input capture or output compare 0 = OC5 enabled 1 = IC4 enabled RTR[1:0] -- Real-Time Interrupt (RTI) Rate Refer to the following table. RTR1 0 0 1 1 RTR0 0 1 0 1 E = 3 MHz 2.731 ms 5.461 ms 10.923 ms 21.845 ms E = 2 MHz 4.096 ms 8.192 ms 16.384 ms 32.768 ms E = 1 MHz 8.192 ms 16.384 ms 32.768 ms 65.536 ms E = X MHz (E/213) (E/214) (E/215) (E/216) MOTOROLA M68HC11E Series Programming Reference Guide 39 M68HC11ERG/AD Parallel I/O Control (PIOC) Address: $1002 Bit 7 Read: Write: Reset: STAF 0 U = Unaffected 6 STAI 0 5 CWOM 0 4 HNDS 0 3 OIN 0 2 PLS U 1 EGA 1 Bit 0 INVB 1 STAF -- Strobe A Interrupt Status Flag STAF is set when the selected edge occurs on strobe A. This bit can be cleared by a read of PIOC with STAF set followed by a read of PORTCL (simple strobed or full input handshake mode) or a write to PORTCL (output handshake mode). 0 = No active edge detected 1 = Selected active edge detected STAI -- Strobe A Interrupt Enable Mask 0 = STAF does not request interrupt 1 = STAF requests interrupt CWOM -- Port C Wired-OR Mode (affects all eight port C pins) 0 = Port C outputs are normal CMOS outputs. 1 = Port C outputs are open-drain outputs. HNDS -- Handshake Mode Bit 0 = Simple strobe mode 1 = Full input or output handshake mode OIN -- Output or Input Handshake Select HNDS must be set to 1 for this bit to have meaning. 0 = Input handshake 1 = Output handshake PLS -- Pulsed/Interlocked Handshake Operation HNDS must be set to 1 for this bit to have meaning. When interlocked handshake is selected, strobe B is active until the selected edge of strobe A is detected. 0 = Interlocked handshake 1 = Pulsed handshake (Strobe B pulses high for two E-clock cycles.) EGA -- Active Edge for Strobe A 0 = STRA falling edge selected 1 = STRA rising edge selected INVB -- Invert Strobe B 0 = Active level is logic 0. 1 = Active level is logic 1. 40 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers STAF Clearing Sequence Simple strobed mode Full-input handshake mode Fulloutput handshake mode Read PIOC with STAF = 1 then read PORTCL Read PIOC with STAF = 1 then read PORTCL Read PIOC with STAF = 1 then write PORTCL HNDS OIN PLS EGA Port B Inputs latched into PORTCL on any active edge on STRA Inputs latched into PORTCL on any active edge on STRA Driven as outputs if STRA at active level; follows DDRC if STRA not at active level Port C STRB pulses on writes to PORTB Normal output port, unaffected in handshake modes Normal output port, unaffected in handshake modes 0 0 X X 1 1 0 0 = STRB active level 1 = STRB active pulse 0 = STRB active level 1 = STRB active pulse 1 0 0 1 Port C Driven 1 1 STRA Follow Active Edge Follow DDRC DDRC Port A Data Register (PORTA) Address: $1000 Bit 7 Read: Write: Reset: Alt. Pin Function: And/OR PA7 I PAI OC1 6 PA6 0 OC2 OC1 5 PA5 0 OC3 OC1 4 PA4 0 OC4 OC1 3 PA3 I OC5/IC4 OC1 2 PA2 I IC1 -- 1 PA1 I IC2 -- Bit 0 PA0 I IC3 -- NOTE: I/O pins configured as high-impedance inputs have port data that is indeterminate. The contents of the corresponding latches are dependent upon the electrical state of the pins during reset. This is indicated by an "I" in the port description. Port B Data Register (PORTB) Address: $1004 Bit 7 Read: Write: Reset: Single Chip or Boot: Expanded or Test: PB7 0 PB7 ADDR15 6 PB6 0 PB6 ADDR14 5 PB5 0 PB5 ADDR13 4 PB4 0 PB4 ADDR12 3 PB3 0 PB3 ADDR11 2 PB2 0 PB2 ADDR10 1 PB2 0 PB1 ADDR9 Bit 0 PB0 0 PB0 ADDR8 MOTOROLA M68HC11E Series Programming Reference Guide 41 M68HC11ERG/AD Port C Data Register (PORTC) Address: $1003 Bit 7 Read: Write: Reset: Single Chip or Boot: Expanded or Test: PC7 0 PC7 DATA7 6 PC6 0 PC6 DATA6 5 PC5 0 PC5 DATA5 4 PC4 0 PC4 DATA4 3 PC3 0 PC3 DATA3 2 PC2 0 PC2 DATA2 1 PC2 0 PC1 DATA1 Bit 0 PC0 0 PC0 DATA0 Port C Latched Data Register (PORTCL) Address: $1005 Bit 7 Read: Write: Reset: PCL7 6 PCL6 5 PCL5 4 PCL4 3 PCL3 2 PCL2 1 PCL1 Bit 0 PCL0 Indeterminate after reset Port D Data Register (PORTD) Address: $1008 Bit 7 Read: Write: Reset: Alt. Pin Function 0 -- 0 -- 6 5 PD5 I SS 4 PD4 I SCK 3 PD3 2 PD2 1 PD1 I TxD Bit 0 PD0 I RxD I I SDO/MOSI SDI/MISO = Unimplemented Port E Data Register (PORTE) Address: $100A Bit 7 Read: Write: Reset: Alt. Pin Function PE7 I AN7 6 PE6 I AN6 5 PD5 I AN5 4 PE4 I AN4 3 PE3 I AN3 2 PE2 I AN2 1 PE1 I AN1 Bit 0 PE0 I AN0 EEPROM Programming Control Register (PPROG) Address: $103B Bit 7 Read: Write: Reset: ODD 0 6 EVEN 0 5 ELAT(1) 0 4 BYTE 0 3 ROW 0 2 ERASE 0 1 EELAT 0 Bit 0 EPGM 0 1. MC68HC711E9 and MC68S711E9 only ODD -- Program Odd Rows in Half of EEPROM (TEST) EVEN -- Program Even Rows in Half of EEPROM (Test) Bit 42 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers ELAT -- EPROM/OTPROM Latch Control Implemented on MC68HC711E9 only 0 = EPROM/OTPROM address and data bus configured for normal reads and cannot be programmed 1 = EPROM/OTPROM address and data bus configured for programming and cannot be read BYTE -- Byte/Other EEPROM Erase Mode 0 = Row or bulk erase mode used 1 = Erase only one byte of EEPROM ROW -- Row/All EEPROM Erase Mode Only valid when BYTE = 0 0 = Erase all of EEPROM 1 = Erase only one 16-byte row of EEPROM BYTE 0 0 1 1 ROW 0 1 0 1 Action Bulk erase (all bytes) Row erase (16 bytes) Byte erase Byte erase ERASE -- Erase/Normal Control for EEPROM 0 = Normal read or program mode 1 = Erase mode EELAT -- EEPROM Latch Control 0 = EEPROM address and data bus configured for normal reads 1 = EEPROM address and data bus configured for programming or erasing EPGM --EPROM/EEPROM Programming Voltage Enable 0 = Programming voltage to array disconnected (EEPROM only on MC68HC(7)11E20) 1 = Programming voltage to array connected (EEPROM only on MC68HC(7)11E20) Serial Communication Interface Control Register 1 (SCCR1) Address: $102C Bit 7 Read: Write: Reset: R8 I 6 T8 I 0 = Unimplemented 5 4 M 0 0 0 0 0 3 2 1 Bit 0 R8 -- Receive Data Bit 8 0 = SCI receiver configured for 8-bit data characters. 1 = If M bit is set, R8 stores the ninth data bit in the receive data character. MOTOROLA M68HC11E Series Programming Reference Guide 43 M68HC11ERG/AD T8 -- Transmit Data Bit 8 0 = SCI transmitter configured for 8-bit data characters. 1 = If M bit is set, R8 stores the ninth data bit in the transmit data character. Bit 5 -- Unimplemented Always reads 0 M -- Mode Bit (select character format) 0 = Start bit, 8 data bits, 1 stop bit 1 = Start bit, 9 data bits, 1 stop bit WAKE -- Wakeup by Address Mark/Idle 0 = Wakeup by IDLE line recognition 1 = Wakeup by address mark (most significant data bit set) Bits [2:0] -- Unimplemented Always read 0 Serial Communications Interface Control Register 2 (SCCR2) Address: $102D Bit 7 Read: Write: Reset: TIE 0 6 TCIE 0 5 RIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0 Bit 0 SBK 0 TIE -- Transmit Interrupt Enable 0 = TDRE interrupts disabled 1 = SCI interrupt requested when TDRE status flag is set TCIE -- Transmit Complete Interrupt Enable 0 = TC interrupts disabled 1 = SCI interrupt requested when TC status flag is set RIE -- Receiver Interrupt Enable 0 = RDRF and OR interrupts disabled 1 = SCI interrupt requested when RDRF flag or the OR status flag is set ILIE -- Idle-Line Interrupt Enable 0 = IDLE interrupts disabled 1 = SCI interrupt requested when IDLE status flag is set TE -- Transmitter Enable 0 = Transmitter disabled 1 = Transmitter enabled RE -- Receiver Enable 0 = Receiver disabled 1 = Receiver enabled RWU -- Receiver Wakeup Control 0 = Normal SCI receiver 1 = Wakeup enabled and receiver interrupts inhibited SBK -- Send Break 0 = Break generator off 1 = Break codes generated as long as SBK = 1 44 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers Serial Communications Interface Data Register (SCDR) Address: $102F Bit 7 Read: Write: Reset: R7/T7 I 6 R6/T6 I 5 R5/T5 I 4 R4/T4 I 3 R3/T3 I 2 R2/T2 I 1 R1/T1 I Bit 0 R0/T0 I R[7:0]/T[7:0] -- Receiver/Transmitter Data Bits [7:0] Receive and transmit are double buffered. Reads access the receive data buffer, and writes access the transmit data buffer. When the M bit in SCCR1 is set, R8 and T8 in SCCR1 store the ninth bit in receive and transmit data characters. Serial Communications Interface Status Register (SCSR) Address: $102E Bit 7 Read: Write: Reset: TDRE 1 6 TC 1 = Unimplemented 5 RDRF 0 4 IDLE 0 3 OR 0 2 NF 0 1 FE 0 0 Bit 0 TDRE -- Transmit Data Register Empty Flag This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and then writing to SCDR. 0 = SCDR busy 1 = SCDR empty TC -- Transmit Complete Flag This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear the TC flag by reading SCSR with TC set and then writing to SCDR. 0 = Transmitter busy 1 = Transmitter idle RDRF -- Receive Data Register Full Flag This flag is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading SCSR with RDRF set and then reading SCDR. 0 = SCDR empty 1 = SCDR full IDLE -- Idle Line Detected Flag This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has been active and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR with IDLE set and then reading SCDR. 0 = RxD line active 1 = RxD line idle MOTOROLA M68HC11E Series Programming Reference Guide 45 M68HC11ERG/AD OR -- Overrun Error Flag OR is set if a new character is received before a previously received character is read from SCDR. Clear the OR flag by reading SCSR with OR set and then reading SCDR. 0 = No overrun 1 = Overrun detected NF -- Noise Error Flag NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading SCSR with NF set and then reading SCDR. 0 = Unanimous decision 1 = Noise detected FE -- Framing Error Flag FE is set when a 0 is detected where a stop bit was expected. Clear the FE flag by reading SCSR with FE set and then reading SCDR. 0 = Stop bit detected 1 = Zero detected Bit 0 -- Unimplemented Always reads 0 Serial Peripheral Interface Control Register (SPCR) Address: $1028 Bit 7 Read: Write: Reset: SPIE 0 6 SPE 0 5 DWOM 0 4 MSTR 0 3 CPOL 0 2 CPHA 1 1 SPR1 U Bit 0 SPR0 U SPIE -- Serial Peripheral Interrupt Enable 0 = SPI interrupts disabled 1 = SPI interrupts enabled SPE -- Serial Peripheral System Enable 0 = SPI off 1 = SPI on DWOM -- Port D Wired-OR Mode Option for Port D Pins PD[5:0] 0 = Normal CMOS outputs 1 = Open-drain outputs MSTR -- Master Mode Select 0 = Slave mode 1 = Master mode CPOL, CPHA -- Clock Polarity, Clock Phase Refer to Figure 7 SPR[1:0] -- SPI Clock Rate Select See the following table. 46 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers SPR1 SPR0 0 0 1 1 0 1 0 1 Divide E Clock By 2 4 16 32 Frequency at E = 1 MHz (Baud) 500 kHz 250 kHz 62.5 kHz 31.3 kHz Frequency at E = 2 MHz (Baud) 1.0 MHz 500 kHz 125 kHz 62.5 kHz Frequency at E = 3 MHz (Baud) 1.5 MHz 750 kHz 187.5 kHz 93.8 kHz Frequency at E = 4 MHz (Baud) 2 MHz 1 MHz 250 kHz 125 kHz SCK CYCLE # SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE INPUT (CPHA = 0) DATA OUT SAMPLE INPUT (CPHA = 1) DATA OUT SS (TO SLAVE) MSB 1 2 3 4 5 6 7 8 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB SLAVE CPHA = 1 TRANSFER IN PROGRESS 3 MASTER TRANSFER IN PROGRESS 2 1 1. SS ASSERTED 2. MASTER WRITES TO SPDR 3. FIRST SCK EDGE 4. SPIF SET 5. SS NEGATED SLAVE CPHA = 0 TRANSFER IN PROGRESS 4 5 Figure 7. Serial Peripheral Interface Transfer Format Serial Peripheral Interface Data Register (SPDR) Address: $102A Bit 7 Read: Write: BIT 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 BIT 0 SPI is double buffered in, single buffered out. MOTOROLA M68HC11E Series Programming Reference Guide 47 M68HC11ERG/AD Serial Peripheral Interface Status Register (SPSR) Address: $1029 Bit 7 Read: Write: Reset: SPIF 0 6 WCOL 0 = Unimplemented 0 5 4 MODF 0 0 1 U U 3 2 1 Bit 0 SPIF -- SPI Transfer Complete Flag This flag is set when an SPI transfer is complete (after eight SCK cycles in a data transfer). Clear this flag by reading SPSR (with SPIF = 1), then access SPDR. 0 = No SPI transfer complete or SPI transfer still in progress 1 = SPI transfer complete WCOL -- Write Collision This flag is set if the MCU tries to write data into SPDR while an SPI data transfer is in progress. Clear this flag by reading SPSR (with WCOL = 1), then access SPDR. 0 = No write collision error 1 = SPDR written while SPI transfer in progress Bit 5 -- Unimplemented Always reads 0 MODF -- Mode Fault (Mode fault terminates SPI operation) MODF is set when SS is pulled low while MSTR = 1. Clear this flag by reading SPCR with MODF set, then write to SPCR. 0 = No mode fault error 1 = SS pulled low in master mode Bits [3:0] -- Unimplemented Always reads 0 Timer Count Register (TCNT) Address: $100E -- High Bit 7 Read: BIT 15 Write: Reset: 0 Address: $100F -- Low Bit 7 Read: Write: Reset: BIT 7 0 6 14 0 6 6 5 13 0 5 5 4 12 0 4 4 0 3 11 0 3 3 0 2 10 0 2 2 0 1 9 0 1 1 0 Bit 0 BIT 8 0 Bit 0 BIT 0 0 0 0 = Unimplemeted In normal modes, TCNT is a read-only register. 48 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers Timer Control Register 1 (TCTL1) Address: $1020 Bit 7 Read: Write: Reset: OM2 0 6 OL2 0 5 OM3 0 4 OL3 0 3 OM4 0 2 OL4 0 1 OM5 0 Bit 0 OL5 0 OM[2:5] -- Output Mode OL[2:5] -- Output Level OMx 0 0 1 1 OLx 0 1 0 1 Action Taken on Successful Compare Timer disconnected from output pin logic Toggle OCx output line Clear OCx output line to 0 Set OCx output line to 1 Timer Control Register 2 (TCTL2) Address: $1021 Bit 7 Read: Write: Reset: EDG4B 0 EDGxB 0 0 1 1 6 EDG4A 0 5 EDG1B 0 EDGxA 0 1 0 1 4 EDG1A 0 3 EDG2B 0 2 EDG1B 0 1 EDG3B 0 Bit 0 EDG3A 0 Configuration Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge Factory Test Register (TEST1) Address: $103E Bit 7 Read: Write: Reset: TILOP 0 0 = Unimplemented 6 5 OCCR 0 4 CBYP 0 3 DISR -- 2 FCM 0 1 FCOP 0 Bit 0 TCON 0 TILOP -- Test Illegal Opcode (Test modes only) Bit 6 -- Unimplemented Always reads 0 OCCR -- Output Condition Code Register to Timer Port (Test modes only) CBYP -- Timer Divider Chain Bypass (Test modes only) DISR -- Disable Reset from COP and Clock Monitor (Special modes only (SMOD = 1)) MOTOROLA M68HC11E Series Programming Reference Guide 49 M68HC11ERG/AD FCM -- Force Clock Monitor Failure (Test modes only) FCOP -- Force COP Watchdog Failure (Test modes only) TCON -- Test Configuration (Test modes only) Timer Interrupt Flag 1 Register (TFLG1) Address: $1023 Bit 7 Read: Write: Reset: OC1F 0 6 OC2F 0 5 OC3F 0 4 OC4F 0 3 IR/O5F 0 2 IC1F 0 1 1C2F 0 Bit 0 IC3F 0 Clear flags by writing a 1 to the corresponding bit position(s). OC1FOC4F -- Output Compare x Flag Set each time the counter matches output compare x value. I4/O5F -- Input Capture 4/Output Compare 5 Flag Set by IC4 or OC5, depending on which function was enabled by I4/O5 of PACTL. IC1FIC3F -- Input Capture x Flag Set each time a selected active edge is detected on the ICx input line. Timer Interrupt Flag 2 Register (TFLG2) Address: $1025 Bit 7 Read: Write: Reset: TOF 0 6 RTIF 0 = Unimplemented 5 PAOVF 0 4 PAIF 0 0 0 0 0 3 2 1 Bit 0 Clear flags by writing a 1 to the corresponding bit position(s). TOF -- Timer Overflow Flag Set when TCNT changes from $FFFF to $0000 RTIF -- Real-Time (Periodic) Interrupt Flag The RTIF status bit is automatically set to 1 at the end of every RTI period. To clear RTIF, write a byte to TFLG2 with bit 6 set. PAOVF -- Pulse Accumulator Overflow Flag Set when PACNT changes from $FF to $00 PAIF -- Pulse Accumulator Input Edge Flag Set each time a selected active edge is detected on the PAI input line. Bits [3:0] -- Unimplemented Always reads 0 50 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers Timer Input Capture 4/Output Compare 5 Register (TI4/O5) Address: $101E -- High Bit 7 Read: Write: Reset: BIT 15 1 Bit 7 Read: Write: Reset: BIT 7 1 6 BIT 14 1 6 BIT 6 1 5 BIT 13 1 5 BIT 5 1 4 BIT 12 1 4 BIT 4 1 3 BIT 11 1 3 BIT 3 1 2 BIT 10 1 2 BIT 2 1 1 BIT 9 1 1 BIT 1 1 Bit 0 BIT 8 1 Bit 0 BIT 0 1 Address: $101F -- Low Timer Input Capture Registers (TIC1TIC3) TIC1 -- Address: $1010 -- High Bit 7 Read: Write: Reset: Address: $1011 -- Low Bit 7 Read: Write: Reset: TIC2 -- Address: $1012 -- High Bit 7 Read: Write: Reset: Address: $1013 -- Low Bit 7 Read: Write: Reset: TIC3 -- Address: $1014 -- High Bit 7 Read: Write: Reset: Address: $1015 -- Low Bit 7 Read: Write: Reset: BIT 7 6 BIT 6 5 BIT 5 4 BIT 4 3 BIT 3 2 BIT 2 1 BIT 1 Bit 0 BIT 0 BIT 15 6 BIT 14 5 BIT 13 4 BIT 12 3 BIT 11 2 BIT 10 1 BIT 9 Bit 0 BIT 8 BIT 7 6 BIT 6 5 BIT 5 4 BIT 4 3 BIT 3 2 BIT 2 1 BIT 1 Bit 0 BIT 0 BIT 15 6 BIT 14 5 BIT 13 4 BIT 12 3 BIT 11 2 BIT 10 1 BIT 9 Bit 0 BIT 8 BIT 7 6 BIT 6 5 BIT 5 4 BIT 4 3 BIT 3 2 BIT 2 1 BIT 1 Bit 0 BIT 0 BIT 15 6 BIT 14 5 BIT 13 4 BIT 12 3 BIT 11 2 BIT 10 1 BIT 9 Bit 0 BIT 8 Unaffected by reset Unaffected by reset Unaffected by reset Unaffected by reset Unaffected by reset Unaffected by reset MOTOROLA M68HC11E Series Programming Reference Guide 51 M68HC11ERG/AD Timer Interrupt Mask Register 1 (TMSK1) Address: $1022 Bit 7 Read: Write: Reset: OC1I 0 6 OC2I 0 5 OC3I 0 4 OC4I 0 3 I4/O5I 0 2 IC1I 0 1 IC2I 0 Bit 0 IC3I 0 OC1IOC4I -- Output Compare x Interrupt Enable If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested. I4/O5I -- Input Capture 4/Output Compare 5 Interrupt Enable When I4/O5 in PACTL is 1, I4/O5I is the input capture 4 interrupt enable bit. When I4/O5 in PACTL is 0, I4/O5I is the output compare 5 interrupt enable bit. IC1IIC3I -- Input Capture x Interrupt Enable If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested. Timer Interrupt Mask Register 2 (TMSK2) Address: $1024 Bit 7 Read: Write: Reset: TOI 0 6 RTII 5 PAOVI 4 PAII 0 0 0 3 2 1 PR1 0 Bit 0 PR0 0 0 0 = Unimplemented TOI -- Timer Overflow Interrupt Enable 0 = TOF interrupts enabled 1 = Interrupt requested when TOF is set to 1 RTII -- Real-Time Interrupt Enable 0 = RTIF interrupts disabled 1 = Interrupt requested when RTIF is set to 1 PAOVI -- Pulse Accumulator Input Edge Interrupt Enable 0 = PAOVF interrupts disabled 1 = Interrupt requested when PAOVF is set to 1 PAII -- Pulse Accumulator Input Edge Interrupt Enable 0 = PAIF interrupts disabled 1 = Interrupt requested when PAIF is set to 1 Bits [3:2] -- Unimplemented Always reads 0 PR[1:0] -- Timer Prescaler Select In normal modes, PR1 and PR0 can only be written once, and the write must occur within 64 cycles after reset. PR1 0 0 1 1 PR0 0 1 0 1 Prescaler 1 4 8 16 52 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11E Series Registers Timer Output Compare Registers (TOC1TOC4) TOC1 -- Address: $1016 -- High Bit 7 Read: Write: Reset: BIT 15 1 Bit 7 Read: Write: Reset: BIT 7 1 Bit 7 Read: Write: Reset: BIT 15 1 Bit 7 Read: Write: Reset: BIT 7 1 Bit 7 Read: Write: Reset: BIT 15 1 Bit 7 Read: Write: Reset: BIT 7 1 Bit 7 Read: Write: Reset: Read: Write: Reset: BIT 15 1 Bit 7 BIT 7 1 6 BIT 14 1 6 BIT 6 1 6 BIT 14 1 6 BIT 6 1 6 BIT 14 1 6 BIT 6 1 6 BIT 14 1 6 BIT 6 1 5 BIT 13 1 5 BIT 5 1 5 BIT 13 1 5 BIT 5 1 5 BIT 13 1 5 BIT 5 1 5 BIT 13 1 5 BIT 5 1 4 BIT 12 1 4 BIT 4 1 4 BIT 12 1 4 BIT 4 1 4 BIT 12 1 4 BIT 4 1 4 BIT 12 1 4 BIT 4 1 3 BIT 11 1 3 BIT 3 1 3 BIT 11 1 3 BIT 3 1 3 BIT 11 1 3 BIT 3 1 3 BIT 11 1 3 BIT 3 1 2 BIT 10 1 2 BIT 2 1 2 BIT 10 1 2 BIT 2 1 2 BIT 10 1 2 BIT 2 1 2 BIT 10 1 2 BIT 2 1 1 BIT 9 1 1 BIT 1 1 1 BIT 9 1 1 BIT 1 1 1 BIT 9 1 1 BIT 1 1 1 BIT 9 1 1 BIT 1 1 Bit 0 BIT 8 1 Bit 0 BIT 0 1 Bit 0 BIT 8 1 Bit 0 BIT 0 1 Bit 0 BIT 8 1 Bit 0 BIT 0 1 Bit 0 BIT 8 1 Bit 0 BIT 0 1 Address: $1017 -- Low TOC2 -- Address: $1018 -- High Address: $1019 -- Low TOC3 -- Address: $101A -- High Address: $101B -- Low TOC4 -- Address: $101C -- High MOTOROLA M68HC11E Series Programming Reference Guide 53 M68HC11ERG/AD M68HC11 E Series Pin Assignments 4 STRA/AS 3 MODA/LIR 2 MODB/VSTBY 7 EXTAL 6 STRB/R/W 50 PE7/AN7 49 PE3/AN3 48 PE6/AN6 47 PE2/AN2 46 45 44 43 42 M68HC11 E SERIES 41 40 39 38 37 36 35 34 PE5/AN5 PE1/AN1 PE4/AN4 PE0/AN0 PB0/ADDR8 PB1/ADDR9 PB2/ADDR10 PB3/ADDR11 PB4/ADDR12 PB5/ADDR13 PB6/ADDR14 PB7/ADDR15 PA0/IC3 PA1/IC2 33 XTAL PC0/ADDR0/DATA0 PC1/ADDR1/DATA1 PC2/ADDR2/DATA2 PC3/ADDR3/DATA3 PC4/ADDR4/DATA4 PC5/ADDR5/DATA5 PC6/ADDR6/DATA6 PC7/ADDR7/DATA7 RESET * XIRQ/VPPE IRQ PD0/RxD 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 30 PA4/OC4/OC1 39 38 37 36 35 34 33 32 31 30 29 28 27 PD1/TxD PD3/MOSI PD5/SS VDD 31 PA3/OC5/IC4/OC1 PA6/OC2/OC1 * VPPE applies only to devices with EPROM/OTPROM. Figure 8. Pin Assignments for 52-Pin PLCC and CLCC PA1/IC2 PA2/IC1 PA3/OC5/IC4/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 VDD PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TxD * VPPE applies only to devices with EPROM/OTPROM. Figure 9. Pin Assignments for 52-Pin TQFP 54 M68HC11E Series Programming Reference Guide PE2/AN2 PE6/AN6 PE3/AN3 PE7/AN7 VRL VRH VSS MODB/VSTBY MODA/LIR STRA/AS E STRB/R/W EXTAL 14 15 16 17 18 19 20 21 22 23 24 25 26 PA0/IC3 PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PE0/AN0 PE4/AN4 PE1/AN1 PE5/AN5 1 2 3 4 5 6 7 8 9 10 11 12 13 52 51 50 49 48 47 46 45 44 43 42 41 40 PA5/OC3/OC1 PA7/PAI/OC1 PD2/MISO PD4/SCK M68HC11 E SERIES PD0/RxD IRQ XIRQ/VPPE* RESET PC7/ADDR7/DATA7 PC6/ADDR6/DATA6 PC5/ADDR5/DATA5 PC4/ADDR4/DATA4 PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 PC1/ADDR1/DATA1 PC0/ADDR0/DATA0 XTAL PA2/IC1 32 20 1 VSS 52 VRH 51 VRL 5 E MOTOROLA M68HC11ERG/AD M68HC11 E Series Pin Assignments 64 63 62 61 60 59 58 57 PA0/IC3 NC NC NC PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PE0/AN0 PE4/AN4 PE1/AN1 PE5/AN5 1 2 3 4 5 6 7 8 56 55 54 53 52 51 50 49 PA1/IC2 PA2/IC1 PA3/OC5/IC4/OC1 NC NC PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 VDD PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TxD VSS * VPPE applies only to devices with EPROM/OTPROM. Figure 10. Pin Assignments for 64-Pin QFP MOTOROLA M68HC11E Series Programming Reference Guide PE2/AN2 PE6/AN6 PE3/AN3 PE7/AN7 VRL VRH VSS VSS MODB/VSTBY NC MODA/LIR STRA/AS E STRB/R/W EXTAL NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9 10 11 12 13 14 15 16 M68HC11 E SERIES 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC PD0/RxD IRQ XIRQ/VPPE* NC RESET PC7/ADDR7/DATA7 PC6/ADDR6/DATA6 PC5/ADDR5/DATA5 PC4/ADDR4/DATA4 PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 PC1/ADDR1/DATA1 NC PC0/ADDR0/DATA0 XTAL 55 M68HC11ERG/AD VSS MODB/VSTBY MODA/LIR STRA/AS E STRB/R/W EXTAL XTAL PC0/ADDR0/DATA0 PC1/ADDR1/DATA1 PC2/ADDR2/DATA2 PC3/ADDR3/DATA3 PC4/ADDR4/DATA4 PC5/ADDR5/DATA5 PC6/ADDR6/DATA6 PC7/ADDR7/DATA7 RESET * XIRQ/VPPE IRQ PD0/RxD EVSS PD1/TxD PD2/MISO PD3/MOSI PD4/SCK PD5/SS VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 EVSS VRH VRL PE7/AN7 PE3/AN3 PE6/AN6 PE2/AN2 PE5/AN5 PE1/AN1 PE4/AN4 PE0/AN0 PB0/ADDR8 PB1/ADDR9 PB2/ADDR10 PB3/ADDR11 PB4/ADDR12 PB5/ADDR13 PB6/ADDR14 PB7/ADDR15 PA0/IC3 PA1/IC2 PA2/IC1 PA3/OC5/IC4/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 EVDD M68HC11 E SERIES 42 41 40 39 38 37 36 35 34 33 32 31 30 29 * V PPE applies only to devices with EPROM/OTPROM. Figure 11. Pin Assignments for 56-Pin SDIP 56 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD M68HC11 E Series Pin Assignments PA7/PAI/OC1 PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1 PA3/OC5/IC4/OC1 PA2/IC1 PA1/IC2 PA0/IC3 PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PE0/AN0 PE1/AN1 PE2/AN2 PE3/AN3 VRL VRH VSS MODB/VSTBY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 VDD PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TxD PD0/RxD IRQ XIRQ RESET PC7/ADDR7/DATA7 PC6/ADDR6/DATA6 PC5/ADDR5/DATA5 PC4/ADDR4/DATA4 PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 PC1/ADDR1/DATA1 PC0/ADDR0/DATA0 XTAL EXTAL STRB/R/W E STRA/AS MODA/LIR MC68HC811E2 37 36 35 34 33 32 31 30 29 28 27 26 25 Figure 12. Pin Assignments for 48-Pin DIP (MC68HC811E2) MOTOROLA M68HC11E Series Programming Reference Guide 57 M68HC11ERG/AD Hexadecimal to ASCII Conversion Table 2. Hexadecimal to ASCII Conversion Hex $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F ASCII NUL SOH STX ETX EOT ENQ ACK BEL beep BS back sp HT tab LF linefeed VT FF CR return SO SI DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESCAPE FS GS RS US Hex $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E $3F ASCII SP space ! Hex $40 $41 $42 $43 $44 $45 $46 $47 $48 $49 $4A $4B $4C $4D $4E $4F $50 $51 $52 $53 $54 $55 $56 $57 $58 $59 $5A $5B $5C $5D $5E $5F ASCII @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ under Hex $60 $61 $62 $63 $64 $65 $66 $67 $68 $69 $6A $6B $6C $6D $6E $6F $70 $71 $72 $73 $74 $75 $76 $77 $78 $79 $7A $7B $7C $7D $7E $7F ASCII ` grave a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ " quote # $ % & ` apost. ( ) * + , comma - dash . period / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? DEL delete 58 M68HC11E Series Programming Reference Guide MOTOROLA M68HC11ERG/AD Hexadecimal to Decimal Conversion Hexadecimal to Decimal Conversion To convert a hexadecimal number (up to four hexadecimal digits) to decimal, look up the decimal equivalent of each hexadecimal digit in Table 3. The decimal equivalent of the original hexadecimal number is the sum of the weights found in the table for all hexadecimal digits. Table 3. Hexadecimal to/from Decimal Conversion 15 15 4th Hex Digit Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Decimal 0 4,096 8,192 12,288 16,384 20,480 24,576 28,672 32,768 36,864 40,960 45,056 49,152 53,248 57,344 61,440 12 Bit 11 3rd Hex Digit Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Decimal 0 256 512 768 1,024 1,280 1,536 1,792 2,048 2,304 2,560 2,816 3,072 3,328 3,484 3,840 8 8 7 7 2nd Hex Digit Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Decimal 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 4 Bit 3 1st Hex Digit Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 Decimal to Hexadecimal Conversion To convert a decimal number (up to 65,53510) to hexadecimal, find the largest decimal number in Table 3 that is less than or equal to the number you are converting. The corresponding hexadecimal digit is the most significant hexadecimal digit of the result. Subtract the decimal number found from the original decimal number to get the remaining decimal value. Repeat the procedure using the remaining decimal value for each subsequent hexadecimal digit. MOTOROLA M68HC11E Series Programming Reference Guide 59 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. 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