dr_xc06_v3_1 design rule spec file

dr_xc06_v3_1 design rule spec file - X-FAB Semiconductor...

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X-FAB Semiconductor Foundries Haarbergstraße 67 D-99097 Erfurt Germany phone (++49) 361-427-6663 fax (++49) 361-427-6631 Design Rule Specification XC06 - 0.6 μm Modular CMOS Document DR_06_03 Release 3.1 March 2007 Company Confidential ! Do not print or copy this document without permission of X-FAB Semiconductor Foundries! Strictly controlled.
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Design Rule Specification XC06 DR_06_03 Release 3.1 Page 1 Company Confidential Table of Contents 1. Introduction 5 1.1. Revision 5 1.2. Related Documents 6 1.3. General Notes 6 1.4. Support 7 1.5. Process Family 8 2. General 12 2.1. Layer Overview 12 Design Layers 12 Mask Layers 17 2.2. Definitions 21 2.3. Primitive Devices, Elements 23 2.4. Geometric Relations, Rule Code 29 2.5. General Requirements 30 3. Layer and Device Rules 31 3.1. CORE Module Rules 31 3.1.1. Layer Rules 31 NWELL 31 DIFF, NIMP, PIMP, NDIFF, PDIFF 32 POLY1, GATE 34 CONT 35 MET1 37 VIA 39 MET2 40 NOFILLM, Metal Fill 42 3.1.2. Device Rules 43 nmos4, pmos4 43 qpv5 44 qpa 44 rnwell3 45 rdiffn3, rdiffp3 46 rpoly1 46 rm1 47 rm2 47 csandwt 47 mosvc 48 dn, dp, dnw 49 dprot 49 dnnw18, dnnw30, dnnw40 50 dzap 51 pfuse 52 3.2. ESD Module Rules 53 3.2.1. Layer Rules 53 ESD, ESDDIFF 53 3.2.2. Device Rules 54 nesd 54 3.3. MIDOX, PMV and NGD Module Rules 55 3.3.1. Layer Rules 55 MV 55 HV 56 DIFF, NIMP, PIMP, NDIFF, PDIFF 57 PMVVT 59 NGD 60 NLEAK 61 PLEAK 63 3.3.2. Device Rules 65 nmv 65
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Design Rule Specification XC06 DR_06_03 Release 3.1 Page 2 Company Confidential ngmv 66 ngmmv 67 pmv 68 pgmv 69 pgmmv 70 nhv 71 nhhv 73 3.4. DEPL Module Rules 74 3.4.1. Layer Rules 74 NDIMP 74 3.4.2. Device Rules 75 nmvd 75 nhvd 76 nhhvd 77 3.5. PGD Module Rules 78 3.5.1. Layer Rules 78 PGD 78 PLEAK 78 3.5.2. Device Rules 79 pghv 79 pghhv 80 qpvh 81 qnva 82 qnvo 83 dpg 84 3.6. HVS, HVE, PHVE, ISOMOS and ISOMOSA Module Rules 85 3.6.1. Layer Rules 85 DNWELL 85 SNWELL 86 PWELL 87 NOFIMP 90 CCIMP 91 NLEAK 92 PLEAK 95 3.6.2. Device Rules 98 nmosi, pmosi 98 nmosia 99 phv 100 phva 101 phhv 103 nhve 104 nhvea 105 nhhve 106 phve 107 phhve 108 phvea 109 ndse 111 ndsea 112 jnfet 114 qnve 115 qnvea, qnveb, qnvec 116 qpvhe 117 qpvhea 118 rdnwell3, rpwell3 119 rdiffnpw3, rdiffpdnw3 120 csandw 121 dnpw, dpdnw, ddnw, dsnw, dpw 122 dpwe 123 dph 124 dnsp18, dnsp30, dnsp40 125 dpwd18, dpwd30, dpwd40 126 3.7. CAPRES and LINC Module Rules 127
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Design Rule Specification XC06 DR_06_03 Release 3.1 Page 3 Company Confidential 3.7.1. Layer Rules 127 POLY0 127 CONT 127 LINC 128 NLEAK 128 PLEAK 128 3.7.2. Device Rules 129 rpoly0 129 rpolyh 130 cpoly, cpolylin 131 3.8. SCHOTTKY Module Rules 131 3.8.1. Layer Rules 131 NOPLDD 131 3.8.2. Device Rules 132 dsa 132 3.9. ROM and EEPROM Module Rules 133 3.9.1. Layer Rules 133 TUIMP 133 NLEAK 134 3.9.2. Device Rules 135 ctm 135 ctmw 136 ctp0p1, ctp0p1a, ctp0p1b 137 rom 139 3.10. FLASH Module Rules 139 3.11. OPTO Module Rules 140 3.11.1. Layer Rules 140 OPTO 140 3.11.2. Device Rules 142 phodn, phodp, phodnw, phodn0, phodp0, phodnw0 142 3.12. PIN Module Rules 143 3.12.1. Layer Rules 143 NWELL 143 NOSAPW 144 NLEAK 145 3.12.2. Device Rules 146 dpin, dpin0 146 3.13. METAL3 Module Rules 147 3.13.1. Layer Rules 147 VIA2 147 MET3 148 3.13.2. Device Rules 150 rm3 150 csandwtm 150 3.14. THKMET Module Rules 151 3.14.1. Layer Rules 151 VIAL 151 METL 152 3.14.2. Device Rules 154 rm3l 154 csandwtml 154 3.15. PIMIDE Module Rules 155 3.15.1. Layer Rules 155 NOPIM 155 4. Periphery Rules 156 4.1. PAD Rules 156 PAD 156 Standard Bond /Test Pad 158 MET3 Bond / Test Pad 160 METL Bond / Test Pad 162 Probe Pad 164
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This note was uploaded on 01/30/2011 for the course EE 413 taught by Professor Akın during the Fall '10 term at Middle East Technical University.

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dr_xc06_v3_1 design rule spec file - X-FAB Semiconductor...

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