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standard_cell 2nd lab work - LABORATORYWORK2 TUTORIALS...

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L ABORATORY  W ORK  2 T UTORIALS S S TANDARD TANDARD  C  C ELL ELL  D  D ESIGN ESIGN  C  C ONCEPT ONCEPT Todays   digital   integrated   circuits   are   composed   of   several   hundred   thousands   of   logic   gates,   which  corresponds to millions of transistors. To perform the required tasks several blocks are repeated in more than  one place together with other digital cells. Therefore, all these cells should be designed in such a way that,  when they are put together certain conditions can be met.  The determination of the location of the building blocks in the chip is called "placement". Interconnecting  their I/O and power terminals is called "routing". These two steps are very important in the digital design  and determines the area and speed limitations of the designs in general. Therefore, care must be taken at  these design steps.  In order to form complex circuits (like counters, ALUs, etc.) you need to place a number of primary gates  (like inverters, nand/nor gates). It is possible to place digital gates in a number of ways, but we will use the  simplest method: connecting all the gates in the same row. In other words, digital gates will be placed next to  the others in the same row. For this, a number of requirements should be satisfied: The heights of the cells should be exactly the same.  We will use 30um height . The width of the cells  are variable of course. For simple circuits, width will be small, and for complex circuits it will be  wider. When we place the circuits next to another, we want their power lines (VDD and GND) to be  continuous. For this, the height of these lines should be same and they should cover all the width of  the cell.  We will use a power line height of 4um.  It is possible to put the substrate and n-well contacts under VDD and GND lines as oppose to the  Last updated on 2007-11-16 1
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layout you drew in the first laboratory work (Remember that you had put n-well and substrate  contacts near the transistors). This method is used since it decreases the minimum width of the cell,  and provides better biasing of the substrate and the n-well. If we place two cells next to the other,  their contacts should be connected also. See the example below.  The figure above shows the placement of two different cells. Although the widths of the cells are  different, the cell heights and the power line heights are same providing continuous power line  connection. The substrate and n-well connections are put under VDD and GND lines, and they are  also continuous when the cells are connected. Although it is not seen in the figure, NWELL layer and 
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