Verilog_sample - EE413 Tutorials Sample Verilog HDL Codes...

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EE413 Tutorials Sample Verilog HDL Codes Sample Verilog HDL Codes Sample Verilog HDL Codes The HDL (Hardware Description Language) is used for describing the circuit by codes instead of circuit elements. More specifically, the HDL codes take place of “schematics” in the cadence libraries. For instance, in order to describe a DFF, one should insert the sub-elements like inverters, NAND gates, etc. in the schematics. By using HDL, it is possible to describe the same circuit by typing a number of lines of HDL code. There are mainly 2 hardware description language generations: HDL, and Verilog-HDL. Although both of them are used heavily, we will work on Verilog-HDL, since it is easier, and it is closer to engineering concepts. The Verilog-HDL version embedded in the cadence design environment is called as Verilog- XL. There are 2 ways of writing Verilog-XL codes, one is gate-level, and the other is behavioral. A master-slave D-type Flip Flop This will be a sample for gate-level Verilog-XL code. Gate-level Verilog-XL code is not much different than drawing schematics. The following figure shows the schematics of the DFF, and the Verilog-XL code below that describes this circuit. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. // A master-slave type D-Flip Flop module flop (data, clock, clear, q, qb); input data, clock, clear; output q, qb; // primitive #delay instance-name (output, input1, input2, . ....), nand #10 nd1 (a, data, clock, clear), nd2 (b, ndata, clock), nd4 (d, c, b, clear), nd5 (e, c, nclock), nd6 (f, d, nclock), nd8 (qb, q, f, clear); nand #9 nd3 (c, a, d), nd7 (q, e, qb); not #10 inv1 (ndata, data), inv2 (nclock, clock); endmodule Note that, each node and each component in the schematics have a unique name. The inputs and output of the components are important. For instance the inputs of “nd3” are a and d, and the output is c. Now let's see the code in detail. 1. The first line is the comment line. 2. This line describes the name of the circuit. The format is as below: module <circuit_name> ( <pin1>,<pin2>,. ..,<pin n>); module is the keyword. The name of the circuit here is flop, and there are 5 pins with METU MEMS-VLSI Research Group – 2003 1 Last updated on 12/12/2003
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EE413 Tutorials Sample Verilog HDL Codes corresponding names. Note that the direction of the pins (either input or output) are not described yet. 3. This line describes the input pins, and its format is as below: input <pin 1>, <pin 2>,. .., <pin k>; According to the format above, data , clock , and clear pins are input pins. 4. Similar to line 3, this line describes the output pins. So q and qb are the output pins. 6. Now the description of the circuit starts. For the lines from 6 to 15, the following format is valid: <primitive_gate> <delay_time> <name> (<out>, <in1>,<in2>. ..); This line inserts a component with type of primitive_gate having a transition time of delay_time . The name of the component is
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This note was uploaded on 01/30/2011 for the course EE 413 taught by Professor Akın during the Fall '10 term at Middle East Technical University.

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Verilog_sample - EE413 Tutorials Sample Verilog HDL Codes...

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