VerilogXL - EE413 Tutorials Verilog-XL Simulation Tutorial...

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EE413 Tutorials Verilog-XL Simulation Tutorial Verilog-XL Simulation Tutorial Verilog-XL Simulation Tutorial In this tutorial, the simulation of a 4-bit counter will be carried out. The emphasis will be on the Verilog-XL simulator. The 1-bit counter cell will be defined directly using behavioural Verilog-HDL, and the rest will be implemented by schematics. To start with, we should create the Verilog-HDL model of the CNT1 cell. This is done exactly in the same way as we open a new schematic or layout view for an already open cell. Lets assume that we have a cell CNT1 in our library. Click on File->New->Cell View and choose Verilog-Editor as the Tool. View Name will be “functional” automatically. Functional view name is reserved for Verilog-XL views. The fields in the coming pop-up window should look like this given on the right. When you press OK, then the pop-up window will disaapear and the DTPAD editor will be invoked to edit the content of the newly opened functional view 1 . As mentioned before, we will model the CNT1 using behavioral description. It is strongly advised that you examine the following code and understand it very well. Although it may look very simple, it includes some very important features of Verilog HDL, such as function definition, concatanation, assignments, etc. .. And as a final remark, please use similar indentations in your code as well in order to make the code more easy to follow. // Verilog HDL for "EE413", "PLCNT1" "functional" module PLCNT1 (Q, QN, To, CLK, D, L, RB, Ti); output Q, QN, To; input CLK, D, L, RB, Ti; reg q, tout; function mux; input [3:0] in; input [1:0] s; case (s) 2'b00: mux=in[0]; 2'b01: mux=in[1]; 2'b10: mux=in[2]; 2'b11: mux=in[3]; endcase endfunction always @ (RB) begin if (!RB) assign q=1'b0; else deassign q; end always @ ( posedge CLK) q=mux({D,D,~q,q},{L,Ti}); always @ (Ti or q) tout=Ti&q; assign To=tout; assign Q=q; assign QN=~q; endmodule 1If another editor such as " vi " is called, then edit your .tcshrc file and change the EDITOR variable to /usr/dt/bin/dtpad . METU MEMS-VLSI Research Group – 2003 1 Last updated on 12/12/2003
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EE413 Tutorials Verilog-XL Simulation Tutorial After pressing save and closing the editor window, the code that you have entered will be parsed, and if there exists any, the errors will be displayed. As in any compiler, you should try to fix those errors as they have appered, since sometimes one error triggers more than one error. After you have completed the code editing without any errors, and there is no symbol view of that particular cell, then you will be prompted whether to create the symbol view or not. Click on YES in order to create a symbol view
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This note was uploaded on 01/30/2011 for the course EE 413 taught by Professor Akın during the Fall '10 term at Middle East Technical University.

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VerilogXL - EE413 Tutorials Verilog-XL Simulation Tutorial...

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