hw6_soln_2009_final corrections

# hw6_soln_2009_final corrections - a’bd b F = a’b’c’...

This preview shows pages 1–3. Sign up to view the full content.

Homework #6 Solutions ECE 15A, Winter 2009 1) Z = BF + CEF + ACDF 2) NAND Only 3) NOR Only

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
4) Realize Z=A[BC’+D+E(F’+GH)] using NOR gates. 5) F(a,b,c,d) = Σm(0,1,5,7,10,11,14,15) a) 1 st minimum solution by solving K-map gives, F = a’b’c’ + a’bd + ac The two hazards are due to the following covers: - a’b’c and ac - a’bd and ac To eliminate the hazards the following terms are added to F: Therefore F = a’b’c’ + a’bd + ac + bcd + a’c’d The 2 nd minimum solution is F = a’b’c’ + a’c’d + bcd + ac The hazard is due to the following covers: - a’c’d and bcd To eliminate the hazard the following term is added and F becomes, F = a’b’c’ + a’c’d + bcd + ac +
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: a’bd b) F = a’b’c’ + a’c’d + bcd + ac + a’bd The above expression is an AND – OR circuit realization for F. c) F = (a’ + c)(b’ + c + d)(a + b’ + d)(a + c’ + d)(a + b + c’) The above expression is an OR – AND circuit realization for F. 6) A = B = C = 1, so F = (A + B’ + C’)(A’ + B + C’)(A’+ B’ + C) = 1 But, in the figure, gate 4 outputs F = 0, indicating that something is wrong. For the last NOR gate, F = 1 only when all its inputs are 0. But the output of the gate is 1. Therefore, gate 4 is working properly, but gate 1 is connected incorrectly or is malfunctioning. 7) e is the output of the inverter...
View Full Document

{[ snackBarMessage ]}

### Page1 / 3

hw6_soln_2009_final corrections - a’bd b F = a’b’c’...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online